proj-plbook-plChAssemblyMinimalisticIsa

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Table of Contents for Programming Languages: a survey

Minimalistic and pedagogical Assembly Language ISAs

LMC (Little Man Computer)

pedagogical

http://teaching.idallen.com/dat2343/10f/notes/301_LMC.html

https://en.wikipedia.org/wiki/Little_man_computer

" Instructions Numeric code Mnemonic code Instruction Description 1xx ADD ADD Add the value stored in mailbox xx to whatever value is currently on the accumulator (calculator).

    Note: the contents of the mailbox are not changed, and the actions of the accumulator (calculator) are not defined for add instructions that cause sums larger than 3 digits.

2xx SUB SUBTRACT Subtract the value stored in mailbox xx from whatever value is currently on the accumulator (calculator).

    Note: the contents of the mailbox are not changed, and the actions of the accumulator are not defined for subtract instructions that cause negative results - however, a negative flag will be set so that 8xx (BRP) can be used properly.

3xx STA STORE Store the contents of the accumulator in mailbox xx (destructive).

    Note: the contents of the accumulator (calculator) are not changed (non-destructive), but contents of mailbox are replaced regardless of what was in there (destructive)

5xx LDA LOAD Load the value from mailbox xx (non-destructive) and enter it in the accumulator (destructive). 6xx BRA BRANCH (unconditional) Set the program counter to the given address (value xx). That is, value xx will be the next instruction executed. 7xx BRZ BRANCH IF ZERO (conditional) If the accumulator (calculator) contains the value 000, set the program counter to the value xx. Otherwise, do nothing.

    Note: since the program is stored in memory, data and program instructions all have the same address/location format.

8xx BRP BRANCH IF POSITIVE (conditional) If the accumulator (calculator) is 0 or positive, set the program counter to the value xx. Otherwise, do nothing.

    Note: since the program is stored in memory, data and program instructions all have the same address/location format.

901 INP INPUT Go to the INBOX, fetch the value from the user, and put it in the accumulator (calculator)

    Note: this will overwrite whatever value was in the accumulator (destructive)

902 OUT OUTPUT Copy the value from the accumulator (calculator) to the OUTBOX.

    Note: the contents of the accumulator are not changed (non-destructive).

000 HLT/COB HALT/COFFEE BREAK Stop working. DAT DATA This is an assembler instruction which simply loads the value into the next available mailbox. DAT can also be used in conjunction with labels to declare variables. For example, DAT 984 will store the value 984 into a mailbox. "

CARDIAC

" CARDIAC had a 10 instruction machine language. An instruction consisted of three decimal digits (the sign is ignored). The first digit was the op code (O), the second and third digits comprised an address (A). Addressing was one of accumulator to memory absolute, absolute memory to accumulator, input to absolute memory and absolute memory to output.

    OAA

High level languages were never developed for CARDIAC, since they would defeat one of the purposes of the device, to introduce concepts of assembly language programming.

Programs were hand assembled, then written, by pencil into the appropriate memory cells. Instruction Set CARDIAC Instruction Set Opcode Mnemonic Instruction Description 0 INP Input take a number from the input card and put it in a specified memory cell. 1 CLA Clear and add clear the accumulator and add the contents of a memory cell to the accumulator. 2 ADD Add add the contents of a memory cell to the accumulator. 3 TAC Test accumulator contents performs a sign test on the contents of the accumulator; if minus, jump to a specified memory cell. 4 SFT Shift shifts the accumulator x places left, then y places right, where x is the upper address digit and y is the lower. 5 OUT Output take a number from the specified memory cell and write it on the output card. 6 STO Store copy the contents of the accumulator into a specified memory cell. 7 SUB Subtract subtract the contents of a specified memory cell from the accumulator. 8 JMP Jump jump to a specified memory cell. The current cell number is written in cell 99. This allows for one level of subroutines. 9 HRS Halt and reset move bug to the specified cell, then stop program execution. " -- [1]

Knuth's MMIX

https://en.wikipedia.org/wiki/MMIX

Knuth's pedagogical language

64-bit addressing, 64-bit words, 256 general-purpose registers, 32 special-purpose registers. Von Neumann architecture (code and data are in the same memory space).

Instructions:

(tombdo others too, eg MUX, SADD, MOR, MXOR)

Links:

Wirth's RISC

http://www.inf.ethz.ch/personal/wirth/FPGA-relatedWork/RISC-Arch.pdf

Part of the Oberon System.

32-bit words. 16 registers (32-bits each). 32-bit addressing (byte addressing, not word); branch instructions with immediate offsets have 24-bit offsets; load and store memory address offsets are 20 bits; other immediate constants are 16 bits. Note that the largest memory size this has apparently been used for is 'RISC5' which is 1M (20 bit addressing). 32-bit instructions. 5 (4?) instruction encoding formats.

4 ALU condition codes (flag bits): N, Z, C, V (Negative, Zero, Carry, Overflow).

Instructions:

Z), less than (N != V), less or equal ((N != V)Z), true/always; and the negation of each of these conditions.

All instructions have a register direct mode; all except float-point ones have an immediate mode.

Emulators:

DLX

https://en.wikipedia.org/wiki/DLX

since this is closely related to MIPS, it is discussed in chapter The MIPS and DLX, etc, ISAs

Mano machine

https://en.wikipedia.org/wiki/Mano_machine

SIC

https://en.wikipedia.org/wiki/Simplified_Instructional_Computer

OISCs

There are various "one instruction set computers" (OISCs) ( https://en.wikipedia.org/wiki/One_instruction_set_computer ).

SUBLEQ

The 'universal instructions' include subleq ("SUbtract and Branch if Less than or EQual to zero"), which requires 3 operands.

SUBLEQ2

There is also subleq2, which uses an accumulator and requires only 2 operands.

Looking at https://en.wikipedia.org/wiki/One_instruction_set_computer#Synthesized_instructions , we see that at least three 'registers' are needed for simple computations with subleq2. Note however that memory-memory addressing is assumed; if we actually used registers, we'd also need an indirect addressing mode or LOADs and STORES or some other way to reach main memory. The example given for flipping bits also uses an immediate-mode operand of -1 (it would take 2 bits to represent -1,0,1,2).

SUBNEG

'subneg' ("SUbtract and Branch if NEGative"), with three operands

RSSB

rssb (Reverse Subtract and Skip if Borrow), which has only one operand but also uses an accumulator.

Transport triggered architecture

https://en.wikipedia.org/wiki/One_instruction_set_computer also mentions Transport triggered architecture, in which there is only MOV but certain memory locations have magic side effects including arithmetic.

MOV-only OISC on x86

http://www.cl.cam.ac.uk/~sd601/papers/mov.pdf

Nock

Nock is a near-minimalistic 'functional assembly language'. See Target languages.

CPU0

TinyVM

https://github.com/jakogut/tinyvm/blob/v1.0/SYNTAX https://github.com/jakogut/tinyvm/blob/master/include/tvm/tvm.h

"9 registers, modeled after x86 registers":

(plus the FLAGS register?)

Instructions

Links:

JSVM

https://github.com/jawb/JSVM

Instructions:

Assembler has labels and variable names.

Gpfault's SVM

A simple stack machine VM written as a personal exercise. 32-bits word size.

Instructions:

Sample code:

IN ; read integer "A" from standard input
IN ; read integer "B" from standard input

:GCD ; this is a label
DUP ; if B is 0 then A is the gcd
0 ; (immediate values get pushed on the stack)
@END ; (this is how you put the address of a label onto the stack)
JE ; (this will jump to the address at top of stack if the preceding two values are equal)
SWP ; if B is not 0 then the result is gcd(B, A modulo B)
OVR 
MOD
@GCD
JMP ; recursion!

:END
POP ; remove 0 from top of stack 
OUT ; now the result is at the top, print it.

Links:

IJVM

https://en.wikipedia.org/wiki/IJVM

" Mnemonic Operands Description BIPUSH byte Push a byte onto stack DUP N/A Copy top word on stack and push onto stack ERR N/A Print an error message and halt the simulator GOTO label name Unconditional jump HALT N/A Halt the simulator IADD N/A Pop two words from stack; push their sum IAND N/A Pop two words from stack; push Boolean AND IFEQ label name Pop word from stack and branch if it is zero IFLT label name Pop word from stack and branch if it is less than zero IF_ICMPEQ label name Pop two words from stack and branch if they are equal IINC variable name, byte Add a constant value to a local variable ILOAD variable name Push local variable onto stack IN N/A Reads a character from the keyboard buffer and pushes it onto the stack. If no character is available, 0 is pushed INVOKEVIRTUAL method name Invoke a method, pops object reference and optionally pops arguments from stack. IOR N/A Pop two words from stack; push Boolean OR IRETURN N/A Return from method with integer value ISTORE variable name Pop word from stack and store in local variable ISUB N/A Pop two words from stack; subtract the top word from the second to top word, push the answer; LDC_W constant name Push constant from constant pool onto stack NOP N/A Do nothing OUT N/A Pop word off stack and print it to standard out POP N/A Delete word from top of stack SWAP N/A Swap the two top words on the stack WIDE N/A Prefix instruction; next instruction has a 16-bit index

There's also a set of special ARRAY instructions. Instruction Stack before* Stack after Description NEWARRAY count arrayref Create new array on the heap. The count must be of type int. It is popped off the operand stack. The count represents the number of elements in the array to be created. Based on the Sun JVM-spec. The atype parameter is omitted. IALOAD index. arrayref value Load from int array. The arrayref must be of type reference and must refer to an array whose components are of type int. The index must be of type int. Both arrayref and index are popped from the operand stack. The int value in the component of the array at index is retrieved and pushed onto the operand stack. Part of the Sun JVM Spec. IASTORE value, index, arrayref ... Store into int array. The arrayref must be of type reference and must refer to an array whose components are of type int. Both index and value must be of type int. The arrayref, index, and value are popped from the operand stack. The int value is stored as the component of the array indexed by index. Part of the Sun JVM Spec. W_OUT value ... Pop the value from the stack and write a decimal representation of it to the display. For debugging purposes. Not part of the JVM Spec. "

SmallVM

https://github.com/andrewrothman/SmallVM

"a small virtual machine with focus on educating others about virtual machines."

instructions (quoted from https://github.com/andrewrothman/SmallVM/blob/master/src/opcodes.h ):

Unnamed example simple instruction set in David Jaggar's thesis

From Table 1 on page 10 of [2]

QFTASM

https://github.com/QuestForTetris/tetris-writeup/blob/master/QFTASM_Cogol.md

"

...

...

addressing modes...

examples:

"

Fibonacci sequence in five lines:

0. MLZ -1 1 1; initial value 1. MLZ -1 A2 3; start loop, shift data 2. MLZ -1 A1 2; shift data 3. MLZ -1 0 0; end loop 4. ADD A2 A3 1; branch delay slot, compute next term

This code computes the Fibonacci sequence, with RAM address 1 containing the current term. It quickly overflows after 28657.

Gray code:

0. MLZ -1 5 1; initial value for RAM address to write to 1. SUB A1 5 2; start loop, determine what binary number to covert to Gray code 2. SRL A2 1 3; shift right by 1 3. XOR A2 A3 A1; XOR and store Gray code in destination address 4. SUB B1 42 4; take the Gray code and subtract 42 (101010) 5. MNZ A4 0 0; if the result is not zero (Gray code != 101010) repeat loop 6. ADD A1 1 1; branch delay slot, increment destination address

This program computes Gray code and stores the code in succesive addresses starting at address 5. This program utilizes several important features such as indirect addressing and a conditional jump. It halts once the resultant Gray code is 101010, which happens for input 51 at address 56. "

Coq Asm x86 subset

https://www.microsoft.com/en-us/research/wp-content/uploads/2016/12/coqasm.pdf

Figure 4. Supported instruction set

" Inductive BinOp? :=

Inductive UnaryOp? := Inductive Condition := Inductive Instr := "
OP_ADC OP_ADD OP_AND OP_CMP
OP_OR OP_SBB OP_SUB OP_XOR.
OP_INC OP_DEC OP_NOT OP_NEG.
CC_O CC_B CC_Z CC_BE CC_S CC_P CC_L CC_LE.
UOP d (op: UnaryOp?) (dst: RegMem? d)
BOP d (op: BinOp? ) (ds: DstSrc? d)
BITOP (op: BitOp?) (dst: RegMem? true) (bit: RegImm? false)
TESTOP d (dst: RegMem? d) (src: RegImm? d)
MOVOP d (ds: DstSrc? d)
MOVX (signextend w:bool) (dst: Reg) (src: RegMem? w)
SHIFTOP d (op: ShiftOp?) (dst: RegMem? d) (count: ShiftCount?)
MUL {d} (src: RegMem? d)
IMUL (dst: Reg) (src: RegMem? true)
LEA (reg: Reg) (src: RegMem? true)
JCC (cc: Condition) (cv: bool) (tgt: Tgt)
PUSH (src: Src)
POP (dst: RegMem? true)
CALL (tgt: JmpTgt?)JMP (tgt: JmpTgt?)
CLC STC CMC
RETOP (size: WORD)
OUT (d: bool) (port: BYTE)
IN (d: bool) (port: BYTE)
HLT BADINSTR.

Nga

http://forthworks.com/nga http://forthworks.com/nga/Nga.md http://forth.works/book.html#internals-nga-virtual-machine

A minimalistic virtual machine emulating a dual stack computer with a simple instruction set.

Instructions:

" Nga provides two LIFO stacks. The primary one is for data and the secondary one is used to hold return addresses for subroutine calls. ... I/O is not specified, but Nga does provide for adding this in a modular manner, using three instructions to enumerate, query, and interact with any devices provided. ...

Instructions: 0 nop: does nothing 1 lit <v>: followed by a value to push to the stack 2 dup: duplicates the top item on the stack 3 drop: removes the top item from the stack 4 swap: switches the top and second items on the stack 5 push: moves the top value from the data stack to the address stack 6 pop: moves the top item on the address stack to the data stack 7 jump: moves execution to the address on the top of the stack 8 call: calls a subroutine at the address on the top of the stack 9 ccall: conditional call. It takes two values: a flag and a pointer for an address to jump to if the flag is true. A false flag is zero. Any other value is true. 10 return: ends a subroutine and returns flow to the instruction following the last CALL or CCALL. 11 eq: compares two values for equality and returns a flag 12 neq: compares two values for inequality and returns a flag 13 lt: compares two values for less than and returns a flag 14 gt: compares two values for greater than and returns a flag 15 fetch: takes an address and returns the value stored there. This doubles as a means of introspection into the VM state. Negative addresses correspond to VM queries (-1: Data stack depth, -2: Address stack depth, -3: Maximum Image Size; an implementation may use negative values below -100 for implementation-specific inquiries) 16 store: stores a value into an address 17 add: adds two numbers together 18 sub: subtracts two numbers 19 mul: multiplies two numbers 20 divmod: quotient and remainder 21 and: bitwise AND 22 or: bitwise OR 23 xor: bitwise XOR 24 shift: bitwise arithmetic SHIFT. This takes two values x,y and returns one. If y is positive, this shifts right. If negative, it shifts left. 25 zret: returns from a subroutine if the top item on the stack is zero. If not, it acts like a NOP instead. 26 end: tells Nga that execution should end 27 io_enumerate: pushes a value to the stack indicating the number of provided devices. 28 io_query: takes a value and returns two. The top stack item is an identifer for the type of device attached. The second indicates a device specific version number. 29 io_interact: takes a value indicating the desired device and performs an action with the device " -- http://forthworks.com/nga/Nga.md

Nga's MURI assembler's directives

MURI Input syntax is <directive> <data>.

Directives are a single character:

The runtime assembler in the Retro Forth environment built on top of Nga apparently only has i,d,r.

Pinky processor

https://github.com/tslug/pinky/

" The idea behind the pinky is to have lots of very small, simple processors with bitwise-addressible memory and a little bit of visible local memory, no addressible registers, no cache, and 4 instructions, which are focused on self-modifying code and the idea that they quiesce quickly to a sleep state while possibly being fully implementable with async logic.

They're meant to be interconnected using a serial bus to lots of other pinkies, as a single pinky can't get much done alone.

The core operation of a pinky is the move instruction, which is meant to change data in another move instruction, so that when that next move instruction runs, it's doing a lookup operation. The other important operation is arm, which waits for you to write to an armed address, and when you do, it executes the specified code as soon as it gets to the next wait instruction. The last instruction setN is meant only to change the dynamic length of the instruction set and its operands, which helps optimize code around the working set size. " [3]

I think this is originally by Dave Taylor? [4] [5]

Gray1

The Gray-1, a homebrew CPU exclusively composed of memory

http://web.archive.org/web/20170203220739/http://2x-1.net/ob/gray1/

CollapseOS HAL

https://incoherency.co.uk/collapseos/hal.txt.html

Minimalistic ISAs Links and todos

Batbridge

https://github.com/arrdem/batbridge/blob/master/doc/batbridge.md

Simpletron

http://web.cs.wpi.edu/~jburge/courses/c01/cs2011/lectures/lecture5.pdf

MiniVM and Purr VM

https://github.com/ShawSumma/minivm/

https://github.com/ShawSumma/minivm/blob/main/vm/vm.h

https://github.com/ShawSumma/purr/blob/main/purr/vm/bytecode.d

Mate

https://sing.stanford.edu/site/talks/asplos02levis.pdf https://www.cs.ubc.ca/~krasic/cpsc538a/papers/mate.pdf https://www.cse.wustl.edu/~lu/cse521s/Slides/Mate.pdf

Mate ISA:

Mat ́e ISA 0 halt 1 reset clear stack 2 and push($0 & $1) 3 or push($0

4 shiftr push($0 >> $1) (signed) 5 shiftl push($0 1c8l2 R[t] 7: load addr 2 R[d] <- addr 8: load 2 R[d] <- mem[addr] 9: store 2 mem[addr] <- R[d] A: load indirect 1 R[d] <- mem[R[t]] B: store indirect 1 mem[R[t]] <- R[d] C: branch zero 2 if (R[d] == 0) pc <- addr D: branch positive 2 if (R[d] > 0) pc <- addr E: jump register 1 pc <- R[t] F: jump and link 2 R[d] <- pc; pc <- addr
$1)

Register 0 always 0. Loads from mem[FF] from stdin. Stores to mem[FF] to stdout. " -- [6]

nand2tetris's Hack

https://www.csie.ntu.edu.tw/~cyy/courses/introCS/14fall/lectures/handouts/lec08_HackML_4up.pdf Chapter 4: Machine language

" Registers: D, A, M, where M stands for RAM[A] ... Hack commands: A-command: @value set A to value C-command: dest = comp ; jump dest = and ;jump are optional Where: comp = 0 , 1 , ‐1 , D , A , !D , !A , ‐D , ‐A , D+1 , A+1 , D‐1, A‐1 , D+A , D‐A? , A‐D? , D&A , D

M‐D? , D&M , Ddest = M, D, A, MD, AM, AD, AMD, or null jump = JGT , JEQ , JGE , JLT , JNE , JLE , JMP, or null In the command dest = comp; jump, the jump materialzes if (comp jump 0) is true. For example, in D=D+1,JLT, we jump if D+1 < 0. " -- [7]
A , M , !M , ‐M ,M+1, M‐1 , D+M , D‐M? ,
M

encoding: " Translating / assembling A-instructions... 0 v v v v v v v v v v v v v v v

...

Translating / assembling C-instructions comp dest jump 1 1 1 a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3

...

The translation of each of the three fields comp, dest, jump to their binary forms is specified in the following three tables. comp (when a=0) c1 c2 c3 c4 c5 c6 comp (when a=1) 0

1
1 0 1 0 1 0
1 1 1 1 1 1
D A !D !A -D -A D+1A+1D-1A-1D+AD-AA-DD&AD
1 1 1 1 0 10
0 0 1 1 0 0
1 1 0 0 0 0M
0 0 1 1 0 1
1 1 0 0 0 1!M
0 0 1 1 1 1
1 1 0 0 1 1-M
0 1 1 1 1 1
1 1 0 1 1 1M+1
0 0 1 1 1 0
1 1 0 0 1 0M-1
0 0 0 0 1 0D+M
0 1 0 0 1 1D-M
0 0 0 1 1 1M-D
0 0 0 0 0 0D&M
A0 1 0 1 0 1DM

dest d1 d2 d3 null 0 0 0 M 0 0 1 D 0 1 0 MD 0 1 1 A 1 0 0 AM 1 0 1 AD 1 1 0 AMD 1 1 1

jump j1 j2 j3 null 0 0 0 JGT 0 0 1 JEQ 0 1 0 JGE 0 1 1 JLT 1 0 0 JNE 1 0 1 JLE 1 1 0

" JMP 1 1 1

-- [8]

https://www.csie.ntu.edu.tw/~cyy/courses/introCS/14fall/lectures/handouts/lec10_HackAssembler_4up.pdf Chapter 6: Assembler

---

Gyo

https://wiki.xxiivv.com/site/gyo.html

educational VM. Designed by the same person who would later design uxn.

---

uvm

https://github.com/maximecb/uvm

https://pointersgonewild.com/2023/02/24/building-a-minimalistic-virtual-machine/

https://github.com/maximecb/uvm/blob/main/doc/design.md

https://github.com/maximecb/uvm/blob/main/doc/syscalls.md

https://github.com/maximecb/uvm/blob/main/vm/src/vm.rs


Footnotes:

1.

 $1) (signed)6 add  push($0 + $1) -- depends on types 8 putled  $0 used as 2-bit cmd + 3-bit oprnd 9 id  push(moteID) 10 inv  push(-$0) 11 copy  copy $0 on top of stack 12 pop  (pop $0) 13 sense  push(sensor($0)) 14 send  send($0) 15 sendr  send($0) with capsule 5 16 cast  push(const($0)) 17 pushm  push(message) 18 movm  push(pull entry off $0) 19 clear  clear($0), don’t pop it 20 son  turn sounder on 21 soff  turn sounder off 22 not  push(~$0) 23 log  logwrite($0) onto stable storage 24 logr  read(line $1 into msg $0) 25 logr2 read(line $0 into msg $1) 26 sets  set shared variable to $0 27 gets  push(shared variable) 28 rand  push 16 bit random number onto stack 29 eq  if $0 == $1, push 1 else 0 30 neq  if $0 != $1, push 1 else 0 31 call  call $0 32 swap  swap $0 and $1 46 forw  forward this code capsule 47 forwo  forward capsule $0 48 usr0 user instruction 0 49 usr1 user instruction 1 50 usr2 user instruction 2 51 usr3 user instruction 3 52 usr4 user instruction 4 53 usr5 user instruction 5 54 usr6 user instruction 6 55 usr7 user instruction 7 58 setgrp  set group id to $0 59 pot  push(potentiometer setting) 60 pots  set radio potentiometer to $0 61 clockc  set clock counter with $0 62 clockf  set clock freq with $0 (0-7) 63 ret  return from subroutine

SCLASS 64 getms push(short xxx from msg header) 72 getmb push(byte xxx from msg header) 80 getfs push(short xxx from frame) 88 getfb push(byte xxx from frame) 96 setms short xxx of msg header = $0 102 setmb byte xxx of msg header = $0 108 setfs short xxx of frame = $0 114 setfb byte xxx of frame = $0

XCLASS 128 pushc push(xxxxxx) (unsigned) 192 blez if ($0 <= 0) jump xxxxxx

PocoVM

https://github.com/gmisail/PocoVM https://github.com/gmisail/PocoVM/blob/master/poco/vm.js

/r/dailyprogrammer 'Tiny' virtual machine challenge

https://blog.jverkamp.com/2013/08/21/a-tiny-virtual-machine-in-racket/

[a] represents a memory address, a represents a literal and [a]? represents that a value can be either.

AND/OR/XOR [a] [b]? NOT [a] MOV [a] [b]? RANDOM [a] ADD/SUB [a] [b]? JMP [x]? JZ [x]? [a]? JEQ/JLS/JGT [x]? [a] [b]? HALT stop the program APRINT/DPRINT [a]? print [a]?

L1VM

https://github.com/koder77/l1vm/ https://github.com/koder77/l1vm/blob/ae3a9e213dadc8bf42a03627d09616875d48cbc2/include/opcodes.h https://midnight-koder.net/blog/l1vm/ https://hackaday.io/project/163741-l1vm

Magic Architecture from Magic-1 Homebrew CPU

https://homebrewcpu.com/architecture.htm

Instr16

https://git.lysator.liu.se/nisse/instr16

CHUNGUS 2

CHUNGUS 2 - A very powerful 1Hz Minecraft CPU https://www.youtube.com/watch?v=FDiapbD0Xfg ISA: https://docs.google.com/spreadsheets/d/10_ZERVmsKr0uqQXXbHxMQW-aBpHn6tl5L6Mn-zm57O4/edit#gid=1803754650 assembler: https://github.com/sammyuri/chungus-2-assembler discussion: https://lobste.rs/s/isyomf/very_powerful_1hz_minecraft_cpu

Other hardware used in video

Instruction Byte 1 Byte 2 Control lines Mnemonic Description Opcode Operands Halt Update flags ALU Writeback A byte 1 A byte 2 B Immediate NOP No-op No No No No No No No No HLT Halt Yes No No No No No No No STS Settings Setting Immediate No No No No No No No No CLI Conditional load Immediate Destination Condition Sign ext. immediate No No Yes Yes No No No Yes JMP Jump Location Yes No No No No No No No CAL Call Location Yes No No No No No No No RET Return Yes No No No No No No No BRH Branch Condition T Location in page No No No No No No No No POI Pointer E Source B No Yes Yes No Yes No Yes No SLD Special register load Destination Register No Yes Yes Yes No No No No PST Port store Source Port address No Yes Yes No Yes No No No PLD Port load Destination Port address Yes Yes Yes Yes No No No No PSH Push stack Source U W Sign extend offset Sometimes Yes Yes No Yes No No No POP Pop stack Destination U W Sign extend offset Sometimes Yes Yes Yes No No No No MST Memory store Source Address Sometimes Yes Yes No Yes No No No MLD Memory load Destination Address Sometimes Yes Yes Yes No No No No LIM Load immediate Destination Immediate No No Yes Yes No No No Yes AIM AND immediate Source/dest Immediate No Yes Yes Yes Yes No No Yes CMP Compare Source Immediate No Yes Yes No Yes No No Yes CMA Compare AND Source Immediate No Yes Yes No Yes No No Yes MOV Move Destination Source A No No Yes Yes No Yes Yes No ADD Add Destination Source A Type Source B No Yes Yes Yes No Yes Yes No SUB Subtract Destination Source A Type Source B No Yes Yes Yes No Yes Yes No ADI Add immediate Destination Source A Sign ext. immediate No Yes Yes Yes No Yes No Yes BIT Bitwise logic Destination Source A Type Source B No Yes Yes Yes No Yes Yes No BNT Inverse bitwise logic Destination Source A Type Source B No Yes Yes Yes No Yes Yes No SHF Barrel shift Destination Source A Type Source B No Yes Yes Yes No Yes Yes No SFI Barrel shift immediate Destination Source A Type Immediate No Yes Yes Yes No Yes No Yes MUL Multiply/divide Destination Source A Type Source B Yes Yes No Yes No Yes Yes No UDH User defined hardware Destination Source A Type Source B Yes Yes No Yes No Yes Yes No UDH User defined hardware Destination Source A Type Source B Yes Yes No Yes No Yes Yes No BCT Bit count Destination Source A Type Immediate Yes Yes No Yes No Yes No Yes

Binary lambda calculus

imp

https://softwarefoundations.cis.upenn.edu/lf-current/Imp.html

uxn and uxntal and varvara

https://100r.co/site/uxn.html https://wiki.xxiivv.com/site/uxntal.html https://100r.co/site/uxn_design.html https://wiki.xxiivv.com/site/varvara.html https://kokorobot.ca/site/uxn.html https://wiki.xxiivv.com/site/uxntal_reference.html https://wiki.xxiivv.com/site/uxntal_cheatsheet.html https://sr.ht/~rabbits/

" There are 32 opcodes, each opcode occupies 5 bits of a byte, the remaining 3 bits are used for the modes of that opcode.

... The keep mode does not consume items from the stack. The return mode operates on the return-stack directly. The short mode will operate on shorts instead of bytes.

The following table indicates the effect of each opcode with the given stack a b c where c was the last item added to the stack. Other items in the table include the Program Counter(PC), Memory(M), Devices(D) and Return Stack(rs). For a more detailed view of the opcodes, see the Uxntal Reference. Stack Memory 0x00 BRK/LIT Break a b c M[PC+1] 0x10 LDZ Load Zeropage a b M[c8] 0x01 INC Increment a b c+1 0x11 STZ Save Zeropage a {M[c8]=b} 0x02 POP Pop a b 0x12 LDR Load Rel a b M[PC+c8] 0x03 DUP Duplicate a b c c 0x13 STR Save Rel a {M[PC+c8]=b} 0x04 NIP Nip a c 0x14 LDA Load Abs a b M[c16] 0x05 SWP Swap a c b 0x15 STA Save Abs a {M[c16]=b} 0x06 OVR Over a b c b 0x16 DEI Device In a b D[c8] 0x07 ROT Rotate b c a 0x17 DEO Device Out a {D[c8]=b} Logic Arithmetic 0x08 EQU Equal a b?c 0x18 ADD Add a b+c 0x09 NEQ NotEqual? a b!c 0x19 SUB Subtract a b-c 0x0a GTH Greater a b>c 0x1a MUL Multiply a b*c 0x0b LTH Lesser a b<c 0x1b DIV Divide a b/c 0x0c JMP Jump a b {PC+=c} 0x1c AND And a b&c 0x0d JCN JumpCond? a {(b8)PC+=c} 0x1d ORA Or a b

0x0e JSR JumpStash? a b {rs.PC PC+=c} 0x1e EOR ExclusiveOr? a b^c 0x0f STH Stash a b {rs.c} 0x1f SFT Shift a b
c

2. c8h " -- [9]

https://wiki.xxiivv.com/site/uxntal_reference.html

Retrospectives:

Opinions:

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nand2tetris's Toy

https://www.csie.ntu.edu.tw/~cyy/courses/introCS/14fall/lectures/handouts/lec06_TOYprogramming.pdf

" Memory.  Stores data and programs.  256 "words." (16 bits each)  Special word for stdin / stdout.

Program counter (PC).  An extra 8-bit register.  Keeps track of next instruction to be executed.

Registers.  Fastest form of storage.  Scratch space during computation.  16 registers. (16 bits each)  Register 0 is always 0.

...

Instructions 0: halt 1: add 2: subtract 3: and 4: xor 5: shift left 6: shift right 7: load address 8: load 9: store A: load indirect B: store indirect C: branch zero D: branch positive E: jump register F: jump and link " -- [11]

encoding: " 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1

Format 2" -- [12]
opcode dest d source s source t
opcode dest d addr

"

  1. Operation Fmt Pseudocode 0: halt 1 exit(0) 1: add 1 R[d] <- R[s] + R[t] 2: subtract 1 R[d] <- R[s] - R[t] 3: and 1 R[d] <- R[s] & R[t] 4: xor 1 R[d] <- R[s] ^ R[t] 5: shift left 1 R[d] <- R[s] << R[t] 6: shift right 1 R[d] <- R[s]