Table of Contents for Programming Languages: a survey

List from http://www.csun.edu/~glaw/ee525/Lecture01Intro.pdf

1. Altera: NIOS II soft-core processor 2. Xilinx: MicroBlaze? soft-core processor 3. ESA: LEON2 soft-core processor 4. Open Cores: OpenRISC? soft-core processor

http://www.embeddedinsights.com/channels/2010/12/10/considerations-for-4-bit-processing/

Smalltalk-like concurrency model

"As RISC computers started being used in embedded applications, the 32-bit fixed format became a liability since cost and hence smaller code are important...Hitachi simply invented a RISC instruction set with a fixed 16-bit format, called SuperH?, for embedded applications (see Appendix K). It has 16 rather than 32 registers to make it fit the narrower format and fewer instructions but otherwise looks like a classic RISC architecture." -- https://www.inkling.com/read/computer-architecture-hennessy-5th/appendix-a/section-a-7

A reconfigurable 'soft-core' processor

http://www.csun.edu/~glaw/ee525/Lecture03Nios.pdf intro

- http://www.eecg.toronto.edu/~moshovos/ECE243-2008/l19-instruction-representation-stored-program.html encoding format

http://www.eecg.toronto.edu/~moshovos/ECE243-2008/l19-instruction-representation-stored-program.html gives three formats for the NIOS II, formats 'I', 'J', and 'R'. The 'I' has a 6-bit opcode, a 16-bit immediate value, and a two 5-bit operands. The 'J' is only used by the CALL instruction, and has a 6-bit opcode and a 26-bit immediate value. The 'R' format has a 6-bit opcode which is always 0x3a, a 6-bit second opcode, and four 5-bit operands which encode registers. An instruction's format is dependent upon its opcode. If the opcode is for 0x00 (call), it's a 'J'. If the opcode is 0x3a, it's a 'R'. Otherwise it's a 'I'. So the I format is useful for immediate values, the J format for jumps, and the R format for registers.

- http://lgjohn.okstate.edu/3213/lectures/nios2isa.pdf grouping of operations by type

http://www.eecg.toronto.edu/~moshovos/ECE243-2008/ch8.instructionreference.pdf http://www.eecg.toronto.edu/~moshovos/ECE243-2008/n2cpu_nii5v1.pdf

http://www.altera.com/literature/hb/nios2/n2cpu_nii51017.pdf list of all opcodes http://www.johnloomis.org/NiosII/cpu/opcodes.html list of all opcodes

https://www.cs.duke.edu/courses/spring09/cps104/Altera/NiosII_Instructions.pdf

Nios II Instructions

add Rdest, Rsrc1, Rsrc2 signed (with overflow) and unsigned (with carry) addition addi Rdest, Rsrc1, IMM16 signed (with overflow) and unsigned (with carry) addition immediate and Rdest, Rsrc1, Rsrc2 AND andhi Rdest, Rsrc1, IMM16 AND immediate into high halfword andi Rdest, Rsrc1, IMM16 AND immediate div Rdest, Rsrc1, Rsrc2 signed divide divu Rdest, Rsrc1, Rsrc2 unsigned divide mul Rdest, Rsrc1, Rsrc2 multiply, store the 32 low-order bits of the product to Rdest muli Rdest, Rsrc1, IMM16 multiply immediate, sign-extend the 16-bit immediate value to 32 bits, store the 32 low-order bits of the product to Rdest mulxss Rdest, Rsrc1, Rsrc2 signed multiply, store the 32 high-order bits of the product to Rdest mulxsu Rdest, Rsrc1, Rsrc2 treat Rsrc1 as a signed integer and Rsrc2 as an unsigned interger, store the 32 high-order bits of the product to Rdest mulxuu Rdest, Rsrc1, Rsrc2 unsigned multiply, store the 32 high-order bits of the product to Rdest nor Rdest, Rsrc1, Rsrc2 bitwise logical nor or Rdest, Rsrc1, Rsrc2 bitwise logical or orhi Rdest, Rsrc1, IMM16 calculate the bitwise logical OR of Rsrc1 and (IMM16:0x0000) and store the result in Rdest ori Rdest, Rsrc1, IMM16 calculate the bitwise logical OR of Rsrc1 and (0x0000:IMM16) and store the result in Rdest rol Rdest, Rsrc1, Rsrc2 rotate Rsrc1 left by the number of bits specified in Rsrc24..0, the bits that shift out of the register rotate into the least-significant bit positions roli Rdest, Rsrc1, IMM5 rotate Rsrc1 left by the number of bits specified in IMM5 ror Rdest, Rsrc1, Rsrc2 rotate Rsrc1 right by the number of bits specified in Rsrc24..0, the bits that shift out of the register rotate into the most-significant bit positions sll Rdest, Rsrc1, Rsrc2 shift Rsrc1 left by the number of bits specified in Rsrc24..0 (inserting zeros) slli Rdest, Rsrc1, IMM5 shift Rsrc1 left by the number of bits specified in IMM5 (inserting zeros) sra Rdest, Rsrc1, Rsrc2 shift Rsrc1 right by the number of bits specified in Rsrc24..0 (duplicating the sign bit) srai Rdest, Rsrc1, IMM5 shift Rsrc1 right by the number of bits specified in IMM5 (duplicating the sign bit) srl Rdest, Rsrc1, Rsrc2 shift Rsrc1 right by the number of bits specified in Rsrc24..0 (inserting zeros) srli Rdest, Rsrc1, IMM5 shift Rsrc1 right by the number of bits specified in IMM5 (inserting zeros) sub Rdest, Rsrc1, Rsrc2 signed (with overflow) and unsigned (with carry) subtraction subi Rdest, Rsrc1, IMM16 signed (with overflow) and unsigned (with carry) subtraction immediate xor Rdest, Rsrc1, Rsrc2 calculate the bitwise logical exclusive XOR of Rsrc1 and Rsrc2 xorhi Rdest, Rsrc1, IMM16 calculate the bitwise logical exclusive XOR of Rsrc1 and (IMM16:0x0000) xori Rdest, Rsrc1, IMM16 calculate the bitwise logical exclusive XOR of Rsrc1 and (0x0000:IMM16)

cmpeq Rdest, Rsrc1, Rsrc2 compare equal, Rdest = 1 if Rsrc1 == Rsrc2; otherwise Rdest = 0 cmpeqi Rdest, Rsrc1, IMM16 sign-extend the 16-bit immediate value IMM16 to 32 bits and compare it to the value of Rsrc1, if equal, Rdest = 1; otherwise Rdest = 0 cmpge Rdest, Rsrc1, Rsrc2 signed compare, if Rsrc1 >= Rsrc2, Rdest = 1; otherwise Rdest = 0 cmpgei Rdest, Rsrc1, IMM16 sign-extend the 16-bit immediate value IMM16 to 32 bits and compare it to the value of Rsrc1, if Rsrc1 >= IMM16, Rdest = 1; otherwise Rdest = 0 cmpgeu Rdest, Rsrc1, Rsrc2 unsigned compare, if Rsrc1 >= Rsrc2, Rdest = 1; otherwise Rdest = 0 cmpgeui Rdest, Rsrc1, IMM16 zero-extend the 16-bit immediate value IMM16 to 32 bits and compare it to the value of Rsrc1, if Rsrc1 >= IMM16, Rdest = 1; otherwise Rdest = 0 cmpgt Rdest, Rsrc1, Rsrc2 signed compare, if Rsrc1 > Rsrc2, Rdest = 1; otherwise Rdest = 0 cmpgti Rdest, Rsrc1, IMMED sign-extend the 16-bit immediate value IMMED to 32 bits and compare it to the value of Rsrc1, if Rsrc1 > IMMED, Rdest = 1; otherwise Rdest = 0 cmpgtu Rdest, Rsrc1, Rsrc2 unsigned compare, if Rsrc1 > Rsrc2, Rdest = 1; otherwise Rdest = 0 cmpgtui Rdest, Rsrc1, IMMED zero-extend the 16-bit immediate value IMMED to 32 bits and compare it to the value of Rsrc1, if Rsrc1 > IMMED, Rdest = 1; otherwise Rdest = 0 cmple Rdest, Rsrc1, Rsrc2 signed compare, if Rsrc1 <= Rsrc2, Rdest = 1; otherwise Rdest = 0 cmplei Rdest, Rsrc1, IMMED sign-extend the 16-bit immediate value IMMED to 32 bits and compare it to the value of Rsrc1, if Rsrc1 <= IMMED, Rdest = 1; otherwise Rdest = 0 cmpleu Rdest, Rsrc1, Rsrc2 unsigned compare, if Rsrc1 <= Rsrc2, Rdest = 1; otherwise Rdest = 0 cmpleui Rdest, Rsrc1, IMMED zero-extend the 16-bit immediate value IMMED to 32 bits and compare it to the value of Rsrc1, if Rsrc1 <= IMMED, Rdest = 1; otherwise Rdest = 0 cmplt Rdest, Rsrc1, Rsrc2 signed compare, if Rsrc1 < Rsrc2, Rdest = 1; otherwise Rdest = 0 cmplti Rdest, Rsrc1, IMM16 sign-extend the 16-bit immediate value IMMED to 32 bits and compare it to the value of Rsrc1, if Rsrc1 < IMM16, Rdest = 1; otherwise Rdest = 0 cmpltu Rdest, Rsrc1, Rsrc2 unsigned compare, if Rsrc1 < Rsrc2, Rdest = 1; otherwise Rdest = 0 cmpltui Rdest, Rsrc1, IMM16 zero-extend the 16-bit immediate value IMMED to 32 bits and compare it to the value of Rsrc1, if Rsrc1 < IMM16, Rdest = 1; otherwise Rdest = 0 cmpne Rdest, Rsrc1, Rsrc2 compare not equal, Rdest = 1 if Rsrc1 == Rsrc2; otherwise Rdest = 0 cmpnei Rdest, Rsrc1, IMM16 sign-extend the 16-bit immediate value IMM16 to 32 bits and compare it to the value of Rsrc1, if not equal, Rdest = 1; otherwise Rdest = 0

beq Rsrc1, Rsrc2, label branch if equal bge Rsrc1, Rsrc2, label signed branch if Rsrc1 greater than or equal to Rsrc2 bgeu Rsrc1, Rsrc2, label unsigned branch if Rsrc1 greater than or equal to Rsrc2 bgt Rsrc1, Rsrc2, label signed branch if Rsrc1 greater than Rsrc2 bgtu Rsrc1, Rsrc2, label unsigned branch if Rsrc1 greater than Rsrc2 ble Rsrc1, Rsrc2, label signed branch if Rsrc1 less than or equal to Rsrc2 bleu Rsrc1, Rsrc2, label unsigned branch if Rsrc1 less than or equal to Rsrc2 blt Rsrc1, Rsrc2, label signed branch if Rsrc1 less than Rsrc2 bltu Rsrc1, Rsrc2, label unsigned branch if Rsrc1 less than Rsrc2 bne Rssrc1, Rsrc2, label branch if not equal br label unconditional branch break debugging breakpoint bret breakpoint return call label call subroutine callr Rsrc1 call subroutine in register, the value in Rsrc1 is the address of the next instruction eret exception return jump Rsrc1 transfer execution to the address contained in Rsrc1 ret return from subroutine

Load byte from memory or I/O peripheral ldb/ldbio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, load the byte into Rdest and sign extend the 8-bit value to 32 bits ldbu/ldbuio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, load the byte into Rdest and zero-extend the 8-bit value to 32 bits

Load half word from memory or I/O peripheral ldh/ldhio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, load the half word into Rdest and sign-extend the 16-bit value to 32 bits ldhu/ldhuio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, load the half word into Rdest and zero-extend the 16-bit value to 32 bits Load word from memory or I/O peripheral ldw/ldwio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, load the word into Rdest

Store byte to memory or I/O peripheral stb/stbio Rsrc1, byte_offset(Rsrc2) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, store the low byte to the memory byte specified by the effective address Store half word from memory or I/O peripheral sth/sthio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, store the low halfword to the memory location specified by the effective address

Store word from memory or I/O peripheral stw/stwio Rdest, byte_offset(Rsrc1) compute the effective byte address specified by the sum of Rsrc1 and byte_offset, store the word to the memory location specified by the effective address

mov Rdest, Rsrc1 move register to register movhi Rdest, IMMED move immediate into high halfword, and clear the lower halfword of Rdest to 0x0000 movi Rdest, IMMED move signed immedtiate into word movia Rdest, label move immediate address into word movui Rdest, IMMED move unsigned immediate into word, and zero-extend the immediate value IMMED to 32 bits

nextpc Rdest store the address of the next instruction to Rdest nop no operation rdctl Rdest, ctlN read from control register wrctl ctlN, Rsrc1 write to control register

http://www.alteraforum.com/forum/archive/index.php/t-12814.html (NIOS I, i think)

opcodes: 0x00 call 0x10 cmplti 0x20 cmpeqi 0x30 cmpltui 0x01 jmpi 0x11 0x21 0x31 0x02 0x12 0x22 0x32 custom 0x03 ldbu 0x13 initda 0x23 ldbuio 0x33 initd 0x04 addi 0x14 ori 0x24 muli 0x34 orhi 0x05 stb 0x15 stw 0x25 stbio 0x35 stwio 0x06 br 0x16 blt 0x26 beq 0x36 bltu 0x07 ldb 0x17 ldw 0x27 ldbio 0x37 ldwio 0x08 cmpgei 0x18 cmpnei 0x28 cmpgeui 0x38 rdprs 0x09 0x19 0x29 0x39 0x0A 0x1A 0x2A 0x3A R-type 0x0B ldhu 0x1B flushda 0x2B ldhuio 0x3B flushd 0x0C andi 0x1C xori 0x2C andhi 0x3C xorhi 0x0D sth 0x1D 0x2D sthio 0x3D 0x0E bge 0x1E bne 0x2E bgeu 0x3E 0x0F ldh 0x1F 0x2F ldhio 0x3F

OPX codes (the second opcode in R-format):

0x00 0x10 cmplt 0x20 cmpeq 0x30 cmpltu 0x01 eret 0x11 0x21 0x31 add 0x02 roli 0x12 slli 0x22 0x32 0x03 rol 0x13 sll 0x23 0x33 0x04 flushp 0x14 wrprs 0x24 divu 0x34 break 0x05 ret 0x15 0x25 div 0x35 0x06 nor 0x16 or 0x26 rdctl 0x36 sync 0x07 mulxuu 0x17 mulxsu 0x27 mul 0x37 0x08 cmpge 0x18 cmpne 0x28 cmpgeu 0x38 0x09 bret 0x19 0x29 initi 0x39 sub 0x0A 0x1A srli 0x2A 0x3A srai 0x0B ror 0x1B srl 0x2B 0x3B sra 0x0C flushi 0x1C nextpc 0x2C 0x3C 0x0D jmp 0x1D callr 0x2D trap 0x3D 0x0E and 0x1E xor 0x2E wrctl 0x3E 0x0F 0x1F mulxss 0x2F 0x3F