Table of Contents for Programming Languages: a survey

todo. " The only field where i have heard the Msp430 is superiour to the AVR is its ULTRA low power use." -- http://www.edaboard.com/thread28030.html

" The place the MSP430 really shines, and the thing TI promotes the most about it is its super low current drain. With a 16-bit core that includes multiply and divide instructions, you have a LOT of compute power, yet can achieve a very low current drain" -- http://www.motherboardpoint.com/re-disadvantages-msp430-relative-avr-and-pic-t188117.html

"von Neumann architecture (single address space for code and data)"

" The unified address space, and the orthogonal instruction set, are some of the best features of the msp430 core. "

"

Apart from the JTAG pain, I find the MSP430 to be an excellent family. The last project I did MSP430 was far lower power and far cheaper than the equivalent AVR. I find the low power modes in the MSP much more useful since they wake up in microseconds rather than milliseconds. "

"Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit As field and the 1-bit Ad field." -- https://en.wikipedia.org/wiki/TI_MSP430

" The processor has no exception handling....

"

Single-operand arithmetic:

RRC Rotate right (1 bit) through carry SWPB Swap bytes RRA Rotate right (1 bit) arithmetic SXT Sign extend byte to word PUSH Push value onto stack CALL Subroutine call; push PC and move source to PC RETI Return from interrupt; pop SR then pop PC

Conditional jumps:

JNE/JNZ Jump if not equal/zero JEQ/JZ Jump if equal/zero JNC/JLO Jump if no carry/lower JC/JHS Jump if carry/higher or same JN Jump if negative JGE Jump if greater or equal JL Jump if less JMP Jump (unconditionally)

Two-operand arithmetic:

MOV Move source to destination ADD Add source to destination ADDC Add source and carry to destination SUBC Subtract source from destination (with carry) SUB Subtract source from destination CMP Compare (pretend to subtract) source from destination DADD Decimal add source to destination (with carry) BIT Test bits of source AND destination BIC Bit clear (dest &= ~src) BIS Bit set (logical OR) XOR Exclusive or source with destination AND Logical AND source with destination (dest &= src)

(from https://en.wikipedia.org/wiki/TI_MSP430 )

" MSP430 addressing modes As Ad Register Syntax Description 00 0 n Rn Register direct. The operand is the contents of Rn. 01 1 n x(Rn) Indexed. The operand is in memory at address Rn+x. 10 — n @Rn Register indirect. The operand is in memory at the address held in Rn. 11 — n @Rn+ Indirect autoincrement. As above, then the register is incremented by 1 or 2. Addressing modes using R0 (PC) 01 1 0 (PC) ADDR Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x. 11 — 0 (PC) #x Immediate. Equivalent to @PC+. The operand is the next word in the instruction stream. Addressing modes using R2 (SR) and R3 (CG), special-case decoding 01 1 2 (SR) &ADDR Absolute. The operand is in memory at address x. 10 — 2 (SR) #4 Constant. The operand is the constant 4. 11 — 2 (SR) #8 Constant. The operand is the constant 8. 00 — 3 (CG) #0 Constant. The operand is the constant 0. 01 — 3 (CG) #1 Constant. The operand is the constant 1. There is no index word. 10 — 3 (CG) #2 Constant. The operand is the constant 2. 11 — 3 (CG) #−1 Constant. The operand is the constant −1.

...

MSP430 Emulated instructions Emulated Actual Description

ADC.x dst ADDC.x #0,dst Add carry to destination BR dst MOV dst,PC Branch to destination CLR.x dst MOV.x #0,dst Clear destination CLRC BIC #1,SR Clear carry bit CLRN BIC #4,SR Clear negative bit CLRZ BIC #2,SR Clear zero bit DADC.x dst DADD.x #0,dst Decimal add carry to destination DEC.x dst SUB.x #1,dst Decrement DECD.x dst SUB.x #2,dst Double decrement DINT BIC #8,SR Disable interrupts EINT BIS #8,SR Enable interrupts INC.x dst ADD.x #1,dst Increment INCD.x dst ADD.x #2,dst Double increment INV.x dst XOR.x #−1,dst Invert NOP MOV #0,R3 No operation POP dst MOV @SP+,dst Pop from stack RET MOV @SP+,PC Return from subroutine RLA.x dst ADD.x dst,dst Rotate left arithmetic (shift left 1 bit) RLC.x dst ADDC.x dst,dst Rotate left through carry SBC.x dst SUBC.x #0,dst Subtract borrow (1−carry) from destination SETC BIS #1,SR Set carry bit SETN BIS #4,SR Set negative bit SETZ BIS #2,SR Set zero bit TST.x dst CMP.x #0,dst Test destination " -- https://en.wikipedia.org/wiki/TI_MSP430

Links:

http://www.ti.com/sc/docs/products/micro/msp430/userguid/as_5.pdf http://www.ece.utep.edu/courses/web3376/Links_files/MSP430%20Quick%20Reference.pdf

Addressing modes: immediate, register, absolute, register indirect, (register plus offset) indirect, PC plus offset, register indirect postincrement

ADC(.B) dst dst + C → dst xxxx * ADD(.B) src,dst src + dst → dst xxxx ADDC(.B) src,dst src + dst + C → dst xxxx AND(.B) src,dst src .and. dst → dst 0 x x x BIC(.B) src,dst .not.src .and. dst → dst ---- BIS(.B) src,dst src .or. dst → dst ---- BIT(.B) src,dst src .and. dst 0 x x x BR dst Branch to ....... ---- * CALL dst PC+2→ stack, dst → PC ---- CLR(.B) dst Clear destination ---- * CLRC Clear carry bit ---0 * CLRN Clear negative bit - 0 - - * CLRZ Clear zero bit - - 0 - * CMP(.B) src,dst dst - src xxxx DADC(.B) dst dst + C → dst (decimal) xxxx * DADD(.B) src,dst src + dst + C → dst (decimal) xxxx DEC(.B) dst dst - 1 → dst xxxx * DECD(.B) dst dst - 2 → dst xxxx * DINT Disable interrupt ---- * EINT Enable interrupt ---- * INC(.B) dst Increment destination, dst +1→dst xxxx * INCD(.B) dst Double-Increment destination, dst+2→dst xxxx * INV(.B) dst Invert destination xxxx * JC/JHS Label Jump to Label if Carry-bit is set ---- JEQ/JZ Label Jump to Label if Zero-bit is set ---- JGE Label Jump to Label if (N .XOR. V) = 0 ---- JL Label Jump to Label if (N .XOR. V) = 1 ---- JMP Label Jump to Label unconditionally ---- JN Label Jump to Label if Negative-bit is set ---- JNC/JLO Label Jump to Label if Carry-bit is reset ---- JNE/JNZ Label Jump to Label if Zero-bit is reset ---- MOV(.B) src,dst src→dst ---- NOP No operation ---- * POP(.B) dst Item from stack, SP+2→SP ---- * PUSH(.B) src SP - 2→SP, src→@SP ---- RETI Return from interrupt xxxx TOS→SR?, SP + 2→SPTOS→PC, SP + 2→SZP RET Return from subroutine ---- * TOS→PC?, SP + 2→SP RLA(.B) dst Rotate left arithmetically xxxx * RLC(.B) dst Rotate left through carry xxxx * RRA(.B) dst MSB→MSB? ....LSB→C? 0xxx RRC(.B) dst C→MSB? .........LSB→C? xxxx SBC(.B) dst Subtract carry from destination xxxx * SETC Set carry bit ---1 * SETN Set negative bit - 1 - - * SETZ Set zero bit - - 1 - * SUB(.B) src,dst dst + .not.src + 1→dst xxxx SUBC(.B) src,dst dst + .not.src + C→dst xxxx SWPB dst swap bytes ---- SXT dst Bit7→Bit8 ........ Bit15 0 x x x TST(.B) dst Test destination xxxx * XOR(.B) src,dst src .xor. dst→dst xxxx

Note: Emulated Instructions All marked instructions ( * ) are emulated instructions. The emulated instructions use core instructions combined with the architecture and implementation of the CPU for higher code efficiency and faster execu

Legend: 0 Status bit always cleared 1 Status bit always set x Status bit cleared or set on results - Status bit not affected

- Emulated Instructions

or from wikipedia:

Single-operand arithmetic: RRC Rotate right (1 bit) through carry SWPB Swap bytes RRA Rotate right (1 bit) arithmetic SXT Sign extend byte to word PUSH Push value onto stack CALL Subroutine call; push PC and move source to PC RETI Return from interrupt; pop SR then pop PC

Conditional jump; PC = PC + 2×offset: JNE/JNZ Jump if not equal/zero JEQ/JZ Jump if equal/zero JNC/JLO Jump if no carry/lower JC/JHS Jump if carry/higher or same JN Jump if negative JGE Jump if greater or equal JL Jump if less JMP Jump (unconditionally)

Two-operand arithmetic: MOV Move source to destination ADD Add source to destination ADDC Add source and carry to destination SUBC Subtract source from destination (with carry) SUB Subtract source from destination CMP Compare (pretend to subtract) source from destination DADD Decimal add source to destination (with carry) BIT Test bits of source AND destination BIC Bit clear (dest &= ~src) BIS Bit set (logical OR) XOR Exclusive or source with destination AND Logical AND source with destination (dest &= src)

MSP430 Emulated instructions Emulated Actual Description ADC.x dst ADDC.x #0,dst Add carry to destination BR dst MOV dst,PC Branch to destination CLRC BIC #1,SR Clear carry bit CLRN BIC #4,SR Clear negative bit CLRZ BIC #2,SR Clear zero bit DADC.x dst DADD.x #0,dst Decimal add carry to destination DEC.x dst SUB.x #1,dst Decrement DECD.x dst SUB.x #2,dst Double decrement DINT BIC #8,SR Disable interrupts EINT BIS #8,SR Enable interrupts INC.x dst ADD.x #1,dst Increment INCD.x dst ADD.x #2,dst Double increment INV.x dst XOR.x #−1,dst Invert NOP MOV #0,R3 No operation POP dst MOV @SP+,dst Pop from stack RET MOV @SP+,PC Return from subroutine RLA.x dst ADD.x dst,dst Rotate left arithmetic (shift left 1 bit) RLC.x dst ADDC.x dst,dst Rotate left through carry SBC.x dst SUBC.x #0,dst Subtract borrow (1−carry) from destination SETC BIS #1,SR Set carry bit SETN BIS #4,SR Set negative bit SETZ BIS #2,SR Set zero bit TST.x dst CMP.x #0,dst Test destination

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Links:

- https://courses.cs.washington.edu/courses/cse466/11au/calendar/04-Interrupts-posted.pdf
- http://www.simplyembedded.org/tutorials/msp430-interrupts/

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" samlittlewood 1 day ago [-]

Fun fact - the MSP430 ISA is based on the PDP-11 ISA.

reply

pryelluw 1 day ago [-]

Do you have a source I could read? This is super interesting.

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samlittlewood 1 day ago [-]

Best independent source I can find is http://www.cpushack.com/CPU/cpu4.html#Sec4Part14.

I noticed whilst writing a verilog implementation - seeing the @PC+ relative modes for immediate data made me dig out my PDP-11 reference card.

The number of addressing modes has been halved, gaining a bit for register encoding, and the status register is now in the register file (R2), and R3 is used to generate various constants depending on mode.

Compare and contrast: