proj-plbook-plChIsaComparisons

What is RISC?

Alan Clements wrote a great, well-written, fun to read writeup of RISC. Read that rather than, or at least before, this.

RISC is "Reduced Instruction Set Computer", in contrast to CISC, "Complex Instruction Set Computer". The difference between RISC and CISC is not that RISC necessarily has fewer instructions (although it often does), but rather that RISC instructions are less complex and typically can be executed within a single data memory cycle ( http://en.wikipedia.org/wiki/Reduced_instruction_set_computing#Instruction_set ). Note that this means that RISC instruction sets sometimes eschew operations which access main memory and also do something else, preferring to provide only load/store operations and not other ways of accessing main memory.

The term is not very well defined: "the statement in the 70s about (801/)RISC was that it could be done in a single chip. later in the 80s, (801/)RISC was instructions that could be executed in single machine cycle. Over the decades, the definition of RISC has been somewhat fluid ... especially as the number of circuits in a chip has dramatically increased." -- Lynn Wheeler, https://www.semipublic.comp-arch.net/wiki/RISC_versus_CISC

Here's an attempt to define it:

" what exactly is a RISC processor? This turns out to be quite hard to answer. Here is a list of possible criteria that have been used in the past.

    Instructions are conceptually simple — that is, no baroque things like `evaluate polynomial', or `edit string', both of which were found in the VAX.
    Instructions are uniform length — as opposed, to say, the VAX or M68000 which have a wide range of instruction lengths.
    Instructions use one, or very few, formats — again, unlike the VAX or M68000.
    The instruction set is orthogonal — that is, there are no special rules about what operations are permitted with particular addressing modes (which would complicate the life of a compiler writer).
    There is one, or very few, addressing modes.
    The architecture is load-and-store — that is, only load and store operations access memory — all operate instructions (e.g. arithmetic) only operate on registers.
    The architecture supports two (or perhaps a few more) datatypes — integer and floating point usually." -- http://euler.mat.uson.mx/~havillam/ca/CS323/0708.cs-323004.html

(note:

orthogonality: in processor ISAs, 'orthogonal' seems to refer to:

)

What are popular RISC architectures that might be worth looking at?

As of this writing, ARM is the most commerical successful RISC architecture. Other often-noted ones are SPARC, PowerPC?, and MIPS. Of these, some say that MIPS is the prototypical, most elegant example of RISC:

"MIPS is the cleanest successful RISC. PowerPC? and (32-bit) ARM have so many extra instructions (even a few operating modes, 32-bit ARM especially) that you could almost call them CISC. SPARC has a few odd features and Itanium is composed entirely of odd features. The latter two are more dead than MIPS." -- http://stackoverflow.com/a/2653951/171761

"Answering now your first question: the reason that MIPS features so prominently in books is that it is almost a perfect exemplar of a RISC system. It is a small, relatively pure RISC implementation that is easily understood and that illustrates RISC concepts well. For pedagogical purposes it is probably the best real-world architecture to show the nature of RISC, along with its warts. Other processors thought of as RISC (ARM, SPARC, Alpha, etc.) are more pragmatic and complicated, obfuscating RISC concepts with some more CISC-like enhancements for better performance or other benefits." -- http://stackoverflow.com/a/2796869/171761

"Almost every instruction found in the MIPS core is found in the other architectures" -- http://www.cis.upenn.edu/~milom/cis501-Fall05/papers/RISC-appendix-C.pdf

"MIPS is the most elegant among the effective RISC architectures; even the competition thought so, as evidenced by the strong MIPS influence to be seen in later architectures like DEC’s Alpha and HP’s Precision. Elegance by itself doesn’t get you far in a competitive marketplace, but MIPS microproces- sors have generally managed to be among the most efficient of each generation by remaining among the simplest" --- http://v5.books.elsevier.com/bookscat/samples/9780120884216/9780120884216.PDF

What are popular MCU architectures that might be worth looking at?

In addition, there are 8-bit microcontrollers ("MCUs"), which are not considered in the same class as CPUs but which also have interesting, small intruction sets. The PIC and the AVR architectures are popular ones (the 8051 is also popular but is older, is CISC, and does not seem to be recommended as often; however PIC and AVR are only manufactored by their respective developers, whereas 8051-compatibles are manufactored by a bunch of different companies). Note that Arduino, which you may have heard of, uses AVR or ARM. Many people comment that the AVR is easier to program than the (8-bit) PIC ( http://stackoverflow.com/questions/140049/avr-or-pic-to-start-programming-microcontroller , http://www.ladyada.net/library/picvsavr.html ), but others say that PIC is simpler (e.g. http://www.8051projects.net/lofiversion/t17539/what039s-diff039-between-8051pic-avr.html ); i suspect that they mean that the PIC has fewer instructions and a simpler architecture outside of the ISA, but the AVR has a more uniform architecture and more accessible C compilers, but i'm not too sure what they mean since i've never used either. The PIC and the AVR are both called RISC by some but the AVR has a more RISC-y design (the PIC has indirect addressing), even though it also has a larger instruction set.

AVR, PIC, ARM summary

The AVR, the PIC, and the ARM all have:

mov, jump, call, addition, subtraction, bitwise arithmetic (and/or/not/xor, rotate right, bit clears, NOP, a way to make some hardware-specific calls, branch on zero, branch on condition flag, ways to get and set the condition flags, operands specifying a destination register.

All but the PIC have load/store, relative jumps (higher end PICs have this), <= etc comparisons/branching (higher-end PICs have this), bitwise arithmetic (LSL, LSR, ASR; higher-end PICs have this), negation, carry/no-carry forms of addition and subtraction (higher-end PICs have this), access to the stack pointer (higher-end PICs have this), register indirect addressing for loads (higher-end PICs have this too). AVR Reduced Core and ARM and higher-end PICs have PUSH and POP.

The PIC doesn't have load/store because it memory maps into registers and uses banked memory to deal with the fact that it only has so many registers. The PIC is the only one with banked memory. The ARM doesn't have single instruction bit set/clear until you get to the M3, but the PIC and the AVR do, and they also have a skip/branch-if-bit Only the ARM has MUL (but the AVR Enhanced Core does, as do higher-end PICs), width extension instructions, multiprocessing instructions, multiple registers for load/store/push/pop , byte reversals; it is lacking increment/decrement, and swap nibbles, which the other two do have. Higher-end AVRs and ARMs have post-increment addressing for load/stores. Higher-end ARMs and PICs have multiply-accumulate and division.

Irregularities sometimes seen include not letting anything use immediate (constant) addressing, having an accumulator register with a special role; having to move some things into a certain register first and move it again from there to where you want it, and not having full access to the PC and SP.

In summary, it seems like a reasonable 'common core' would consist of:

mov, jump, call, addition, subtraction, bitwise arithmetic (and/or/not/xor, rotate right, bit clears, NOP, a way to make some hardware-specific calls, branch on zero, branch on condition flag, ways to get and set the condition flags, an operand to specify a destination register for each instruction, load/store, relative jumps, <= etc comparisons/branching, LSL, LSR, ASR, carry/no-carry forms of addition and subtraction, access to the stack pointer, register indirect addressing for loads, PUSH, POP. single instruction bit set/clear, skip/branch-if-bit.

A slightly extended core would also have MUL, post-increment addressing, multiply-accumulate, division, increment, decrement, swap nibbles.

RISC links

Only tangentially of interest:

Summary of major different CPUs and MCU/MCPs

Please note that i know nothing about this stuff and am only repeating what i heard on the web.

timeline:

6502: 1975 PIC: 1975/1985 Z80: 1976 x86: 1978, 1985 (32-bit) 68000: 1979 8051: 1980 MIPS: 1981 ARM: 1986 (ARM6 1992) SPARC: 1987 HC08, HC12: ? PowerPC?: 1992 MCP430: 1993 AVR: 1996

Narrative:

The 6502 was a simple, low-cost CPU; its derivatives were used in Apple IIs and many other machines. It was mentioned in http://www.landley.net/history/mirror/acorn/processors.html .

The PIC MCU family became very popular. It is popular in http://www.embedded.com/electronics-blogs/other/4420311/MCU-popularity--Engineer-vs--provider-perceptions , and mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors , http://www.eejournal.com/archives/articles/20120822-armchoice/ , and indeed almost everywhere.

The Z80 was used in the Sinclair machines and is still a sometimes remarked-upon yet not too popular embedded CPU. It is mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors .

The x86 became the most popular PC CPU. The 486 is the earliest version that modern Debian runs on, although it used to run on 386. It is mentioned almost everywhere.

The 68000 was for a time a major competitor to the x86s. A simplified version remains under the name ColdFire?. It is mentioned in http://www.eejournal.com/archives/articles/20120822-armchoice/

The 8051 MCU became very popular. It is mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors , http://www.eejournal.com/archives/articles/20120822-armchoice/ .

MIPS is a RISC architecture that was once thought to be the future. Is is sometimes described as the "cleanest successful RISC" ( http://stackoverflow.com/questions/2635086/mips-processors-are-they-still-in-use-which-other-architecture-should-i-learn , http://www.cpu-collection.de/?l0=cl&l1=MIPS%20Rx000 ). It is mentioned in http://www.eejournal.com/archives/articles/20120822-armchoice/ .

ARM is the most popular 32-bit CPU architecture. A slightly simplified version is the Cortex M0. It is mentioned almost everywhere, such as http://www.eejournal.com/archives/articles/20120822-armchoice/ .

SPARC is a RISC architecture that was once thought to be the future. It is mentioned in http://www.eejournal.com/archives/articles/20120822-armchoice/ .

HC08 and HC12 evolved from the 6800 family and were popular. This family is popular in http://www.embedded.com/electronics-blogs/other/4420311/MCU-popularity--Engineer-vs--provider-perceptions and mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors.

PowerPC? is a RISC ISA that for a time powered Apple Macintoshes.

MCP430 is a popular and relatively 'clean' 16-bit MCU with low power consumption. It is popular in http://www.embedded.com/electronics-blogs/other/4420311/MCU-popularity--Engineer-vs--provider-perceptions , and mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors.

AVR is a relatively 'clean' 8-bit MCU architecture that is popular with hobbyists (but not so popular in industry). It is somewhat popular in http://www.embedded.com/electronics-blogs/other/4420311/MCU-popularity--Engineer-vs--provider-perceptions , and mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors , and indeed almost everywhere.

The Cypress PSOC is relatively unpopular (later note: actually i heard about it a lot now) but interesting due to its reconfigurable analog and digital blocks, and the the Propeller and the XMOS are unpopular but interesting due to their multiprocessor natures. It is mentioned in http://en.wikibooks.org/wiki/Embedded_Systems/Particular_Microprocessors

One missing piece of data in the above is that Renesas is at the top of the list for MCU revenue yet i can't figure out which of its products are most popular, so i omit them.

Later: in this blog post is a list of popular embedded systems:

    ARM Cortex-M 	
    AVR
    AVR32
    ColdFire
    HC12
    MSP430
    PIC18
    PIC24/dsPIC 	
    PIC32 (MIPS) 	
    PowerPC 	
    RL78 	
    RX100/600 	
    SH 	
    V850 	
    x86 	

The Renesas ones are RL78, RX100/600, SH, V850 (the HC12 is a Freescale (Motorola) processor derived from the 6801). Here's a Google search for those, omitting RX600:

https://www.google.com/search?q=HC12+RL78+RX100+SH+V850

Here's a similar search, but with RX600 instead of RX100: https://www.google.com/search?q=HC12+RL78+RX200+SH+V850

This turns up: http://techon.nikkeibp.co.jp/english/handbook/MCU/handbook_mcu.pdf

which has a discussion of the genealogy Renesas's product lines starting on PDF page 25.

The RL78 is derived from a line of processors from NEC Electronics that originated with a Z80 compatible processor.

Although a line of high-end products was released, the low-end models, the 78K0 and 78K0S (initially called the 78K/0 and 78K/0S), turned out to be pervasive....

"The RL78 was the first product developed by Renesas Electronics after the merger. It combines the 78K0R core and the peripheral circuitry of the R8C. As of March 2011, however, it still uses 78K0R-based peripheral circuitry. A series of products remodeled with the use of R8C-based peripheral circuitry is slated for launch"

The V850 is derived from a line of processors from NEC Electronics that originated with a 8086 compatible processor. "They have been incorporated in various products and are still in use today".

The SH (Super-H) is derived from a Hitachi 32-bit RISC processor. "They are used for SoC? in mobile phones and other devices".

"..the RX family, a line of entirely new CISC-based processors. The company first released a 32-bit processor called the RX600, followed by the 16-bit RX200 processor. The products were designed with the intention to integrate the company’s middle-range CISC architectures into one family in the future. However, the plan was somewhat derailed by the merger with NEC Electronics in 20."

(end 'later:')

here's a Google search for those without the HC12

https://www.google.com/search?q=RL78+RX200+SH+V850

Going by the number of search results found, the last two of those are the least popular. Changing 'SH' to 'superh' is about the same. However, eliminating the first two yields more search results than eliminating the last two. Changing RX200 to RX600 helps. Changing it to RX helps more. Out of RL78 RX superh v850, eliminating the first or the last helps the most (note that many compilers support RX and superh, i guess there is some commonality there). Note that V850 is being replaced by RH850. Replacing V850 with 850 generates more results. Sometimes the RL78 is called 78k. Replacing RL78 with 78 generates more results. Replacing superh with sh (going backwards..) generates more results. Adding the keyword 'renesas' is probably a good idea:

https://www.google.com/search?q=78+RX+sh+850++renesas

Removing RX generates the most results. I also searched for some of these plus "market share". One result was:

One result is http://www.renesasinteractive.com/file.php/1/CoursePDFs/DevCon_On-the-Road/DevCon_On-the-Road/Computing_Architecture/MCU%20R%26D%20Strategies%20for%20the%20Smart%20Society.pdf

but i can't really find the revenue per line for these guys.

As of this writing, the MCP430, PIC, 6800-derivatives, and ARM appear to be the most popular MCUs in industry, and the AVR is the most popular MCU among hobbyists, and ARM and x86 are the most popular CPUs.

The 6502 is probably also worth studying due to its simplicity. ColdFire? is probably also worth studying because some people seem to like it. MIPS is probably also worth studying because people say it is a clean example of a successful RISC. The Cypress PSOC is worth studying because it is intresting, and likewise the Propeller and the XMOS.

So, my list of ISAs to explore is:

The Z80, 8051, SPARC, PowerPC? are left out of this list. They could also be studied if time permits.

Links:

which ones are popular?

archs supported by linux kernel:

as of this writing:

alpha, arc, arm, arm64, avr32, blackfin, c6x, cris, frv, hexagon, ia64, m32r, m68k, metag, microblaze, mips, mn10300, nios2, openrisc, parisc, powerpc, s390, score, sh, sparc, tile, um, unicore32, x86, xtensa [1]

Debian official ports:

amd64, armel, armhf, i386, ia64, kfreebsd, kfreebsd, mips, mipsel, powerpc, s390, s390x, sparc

-- [2]

Debian Unofficial ports:

alpha, arm64, hppa, hurd, m68k, powerpcspe, ppc64, ppc64el, sh4, sparc64, x32

-- [3]

but see also https://www.debian.org/ports/ which has more:

avr32, m32, or1k

consolidating these a little:

alpha, arc, arm, arm64, avr32, blackfin, c6x, cris, frv, hexagon, ia64, m32r, m68k, metag, microblaze, mips, mn10300, nios2, openrisc, parisc, powerpc, s390, score, sh, sparc, tile, um, unicore32, x86, xtensa (TENSILICA XTENSA), [4]

arm, x86, ia-64, mips, powerpc, s390 (z/Architecture), sparc

alpha, hppa, m68k, powerpc, sh4/sh (superH), avr, m32, or1k

some notes on more obscure linux kernel archs:

not surprisingly the Debian ones are a strict subset of the Linux kernel ones (with some renaming)

the combined, consolidated Debian ones are:

alpha, avr, arm, x86, ia-64, m32, m68k, mips, or1k, parisc (HP PA-RISC), powerpc, s390 (z/Architecture), sh (superH), sparc

and the official, consolidated Debian ones are:

arm, ia-64, mips, powerpc, s390 (z/Architecture), sparc, x86

---

http://www.cpushack.com/CPU/cpu.html

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A Survey of RISC Architectures for Desktop, Server, and Embedded Computers by Steven Przybylskic

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http://www.forwardcom.info/comparison.html

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http://www.agner.org/optimize/calling_conventions.pdf https://en.wikipedia.org/wiki/Calling_convention

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Links

AspenCore? 2017 Embedded Markets Study: top answers for:

Which of the following 8-bit chip families would you consider for your next embedded project?

Microchip PIC: 46% Atmel AVR: 43% STMicroelectronics ST6, ST7, ST8: 18% Freescale HC: 13%

Which of the following 16-bit chip families would you consider for your next embedded project?

Microchip PIC24 / dsPIC: 45% TI MSP430: 42% STMicroelectronics ST9, ST10: 22% Freescale HC16: 15%

Which of the following 32-bit chip families would you consider for your next embedded project?

STMicro STM32 (ARM): 30% Microchip PIC 32-bit (MIPS): 20% Xilinx Zynq (with dual ARM Cortex-A9): 17% Freescale i.MX (ARM): 17%

Which vendor has the best ecosystem for your needs?

Microchip or Atmel (Microchip): 14% Texas Instruments (TI): 14% ST Microelectronics: 11% NXP/Freescale/Qualcom: 11% Xilinx: 5%

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