proj-plbook-plCh6502Isa

Table of Contents for Programming Languages: a survey

MOS 6502

highly recommended:

todo explain

" Registers

The 6502's registers include one 8-bit accumulator register (A), two 8-bit index registers (X and Y), an 8-bit processor status register (P), an 8-bit stack pointer (S), and a 16-bit program counter (PC). The stack's address space is hardwired to memory page $01, i.e. the address range $0100–$01FF (256–511). Software access to the stack is done via four implied addressing mode instructions, whose functions are to push or pop (pull) the accumulator or the processor status register. The same stack is also used for subroutine calls via the JSR (Jump to Subroutine) and RTS (Return from Subroutine) instructions and for interrupt handling. "

better description of registers at: http://skilldrick.github.io/easy6502/

http://www.obelisk.demon.co.uk/6502/registers.html

" Addressing

The chip uses the index and stack registers effectively with several addressing modes, including a fast "direct page" or "zero page" mode, similar to that found on the PDP-8, that accesses memory locations from addresses 0 to 255 with a single 8-bit address (saving the cycle normally required to fetch the high-order byte of the address)—code for the 6502 uses the zero page much as code for other processors would use registers. On some 6502-based microcomputers with an operating system, the OS uses most of zero page, leaving only a handful of locations for the user.

Addressing modes also include implied (1 byte instructions); absolute (3 bytes); indexed absolute (3 bytes); indexed zero-page (2 bytes); relative (2 bytes); accumulator (1); indirect,x and indirect,y (2); and immediate (2). Absolute mode is a general-purpose mode. Branch instructions use a signed 8-bit offset relative to the instruction after the branch; the numerical range -128..127 therefore translates to 128 bytes backward and 127 bytes forward from the instruction following the branch (which is 126 bytes backward and 129 bytes forward from the start of the branch instruction). Accumulator mode uses the accumulator as an effective address, and does not need any operand data. Immediate mode uses an 8-bit literal operand. Indirect addressing

The indirect modes are useful for array processing and other looping. With the 5/6 cycle "(indirect),y" mode, the 8-bit Y register is added to a 16-bit base address read from zero page which is located by a single byte following the opcode. The Y register is therefore an index-register in the sense that it is used to hold an actual index (as opposed to the X register in the 6800 where a base address was directly stored and to which an immediate offset could be added). Incrementing the index register to walk the array byte-wise takes only two additional cycles. With the less frequently used "(indirect,x)" mode the effective address for the operation is found at the zero page address formed by adding the second byte of the instruction to the contents of the X register. Using the indexed modes, the zero page effectively acts as a set of up to 128 additional (though very slow) address registers. "

better description of addressing modes at: http://skilldrick.github.io/easy6502/

" The 6502 is technically not a RISC design, however, as arithmetic operations can read any memory cell (not only zero-page), and some instructions (INC, ROL, etc.) even modify memory (i.e. they are read-modify-write instructions), contrary to the basic load/store philosophy of RISC. Furthermore, orthogonality is equally often associated with "CISC".

instructions: http://www.obelisk.demon.co.uk/6502/instructions.html

http://www.visual6502.org/JSSim/index.html

toread for fun: http://archive.archaeology.org/1107/features/mos_technology_6502_computer_chip_cpu.html

toread for fun: http://www.righto.com/2013/01/a-small-part-of-6502-chip-explained.html

toread for fun: http://research.swtch.com/6502

" Used in such greats as the Apple II, all the Acorn machines, the Orics and more. Somewhat simpler device than the Z80 with fewer instructions, fewer addressing modes and fewer registers. Just the minimum compliment of Accumulator, X and Y in fact. It did have the unique ability though to access the first page of memory (0000h to 00ffh) much faster than the rest of memory.

Many people claim now that the 6502 was the first 'RISC' chip, although there weren't many instructions to 'reduce'. If you stretch the point that zero page fast access was akin to having lots of registers though, that sounds slightly RISC-like. It was completely un-RISC-like in that zero page was only good for storing data (and incrememting, decrememting IIRC), all arithmetic had to be done on the Accumulator, and although X and Y were both 'indexing' registers, there were some sorts of indexing that only X could do, and others that only Y could do. " -- http://www.landley.net/history/mirror/acorn/processors.html

Instruction encoding

Links