Continued from Target Languages Concordance part I

Concordance of instructions supported by two platforms

In addition to the above, instructions or intrinsics for each of the following is provided by two platforms in this study:

Arithmetic:

• instructions to load various higher-level data structure constants such as strings
• constant tables/constant pools
• PC-relative arithmetic
• multiplication with overflow (signed and unsigned, 32- and 64-bit)
• unsigned, 64-bit variants of addition, subtraction, multiplication with overflow
• right rotate
• integer compares: inequality, greater-than-or-equal-to, less-than-or-equal-to,
• floating point compares: inequality, greater-than-or-equal-to
• clz ctz popcnt
• byteswaps
• integer conversions from 8-bit or 16-bit to larger
• floating point:
  • abs
  • ceil, floor, trunc, nearest
  • rounding modes and exception modes
  • classify
  • fused multiply-add
  • pow

Memory access:

• global variable loads/stores
• short instructions to load/store the first 4 variables

Stack ops:

• dup

Atomics and Sync:

• AMOs: SWAP, ADD, AND, OR, XOR, MIN, MAX, MINU, MAXU
• either load-release/store-conditional, or compare-and-swap

Control flow:

• jump with link register
• unconstrained indirect branch
• branches: <0, >=0, unsigned <, unsigned >=
• select
• tail calls
• structured control flow loops
• invoke instructions for object-oriented calling.

Data structures:

• OOP
• strings

Misc:

• cycle counters
• special registers
• memory ops such as memcpy

Arithmetic

Constant loads

LuaJIT?2 and CIL have instructions to load various higher-level data structures such as strings.

JVM and LuaJIT?2 use constant tables/constant pools. (i think that LuaJIT?2's constant load instructions can be used for both immediate constants and constant tables, depending on if their argumens is negative or not). Note: CIL does not have a runtime-accessible constant table; it has a constant table for use at compile-time but "Compilers inspect this information, at compile time, when importing metadata, but the value of the constant itself, if used, becomes embedded into the CIL stream the compiler emits. There are no CIL instructions to access the Constant table at runtime" ([1] section II.22.9, page 216).

JVM provides instructions to push constants of null, or 0,1 sometimes 2, or -1...5, depending on type. CIL provides instructions to load -1..8 to i32 as well as null.

• aconst_null dconst_0 dconst_1 fconst_0 fconst_1 fconst_2 iconst_m1 iconst_0 iconst_1 iconst_2 iconst_3 iconst_4 iconst_5 lconst_0 lconst_1 (JVM)
• ldc ldc_w ldc2_w (JVM)
• kstr (LuaJIT?2)
• ldstr (CIL)
• kdata kshort knum kpri knil (LuaJIT?2)
• ldc.i4.0 ldc.i4.1 ldc.i4.2 ldc.i4.3 ldc.i4.4 ldc.i4.5 ldc.i4.6 ldc.i4.7 ldc.i4.8 ldc.i4.m1 ldc.i4.M1 ldnull (CIL)

PC-relative instructions

RISC-V has an instruction to load PC-relative constant, and ARM has PC-relative addition.

• AUIPC (RISC-V RV32I)
• adr (ARM)

Andreas Olofsson of Adapteva said on a blog that he is "not convinced that ((AUIPC)) is essential" [2], however a commenter, Chris, from the RISC-V project explained that it was useful [3].

Add, subtract, multiply, divide

LLVM, CIL, ARM have 32-bit signed integer addition and subtraction with overflow. Only LLVM, CIL have multiplication with overflow, as well as unsigned and 64-bit variants of addition, subtraction, multiplication with overflow.

LLVM offers 'constrained' floating point operations, which means that the rounding and exception modes are respected when those instructions are used. RISC-V provides a similar facility through its rounding mode and exception mode special registers; except that RISC-V does not provide a floating-point mod/remainder instruction.

integer addition with overflow (64-bit and unsigned variants):

• sadd.with.overflow.* uadd.with.overflow.* (LLVM arithmetic with overflow intrinsics)
• add.ovf add.ovf.un (CIL)

integer subtraction with overflow (64-bit and unsigned variants):

• ssub.with.overflow.* usub.with.overflow.* (LLVM arithmetic with overflow intrinsics)
• sub.ovf sub.ovf.un (CIL)

integer multiplication, lower bits, with overflow:

• smul.with.overflow.* umul.with.overflow.* (LLVM arithmetic with overflow intrinsics)
• mul.ovf mul.ovf.un (CIL)

floating point constrained operations (similar to corresponding RISC-V operations, not shown):

• experimental.constrained.fadd (LLVM intrinsic)
• experimental.constrained.fsub (LLVM intrinsic)
• experimental.constrained.fmul (LLVM intrinsic)
• experimental.constrained.fdiv (LLVM intrinsic)
• experimental.constrained.frem (LLVM intrinsic) (no corresponding RISC-V operation)

Moves (copies)

None.

Shifts

WASM and ARM provide right rotate.

Rotate right:

• i32_rotr, i64_rotr (WASM)
• rotate: rors (ARM)

Logical

None.

Compares

WASM and LLVM provide inequality (integer and floating point), integer greater-than-or-equal-to, less-than-or-equal-to, floating point greater-than-or-equal-to (they also provide that for integer, but so do other platforms, so those are listed above rather than here).

Note that some other platforms provide these operations, but only as branches rather than vanilla compares.

Integer inequality:

• i32.ne i64.ne (WASM)
• icmp ne (LLVM)

Integer greater-than-or-equal-to, less-than-or-equal-to:

• i32_ge_s, i32_ge_u, i64_ge_u, i64_ge_s (WASM)
• i32_le_s, i32_le_u, i64_le_u, i64_le_s (WASM)
• icmp sge, icmp uge, icmp sle, icmp ule (LLVM)

Floating point:

• f32.ne f64.ne f32.ge f64.ge (WASM)
• fcmp (various, including neq ge) (LLVM)

Misc integer arith

CLZ, CTZ, POPCNT are provided by WASM and LLVM (but only as LLVM intrinsics).

LLVM and ARM provide various byteswaps.

• i32.clz, i64.clz (WASM): count leading zeros
• ctlz.* (LLVM intrinsic)
• i32.ctz, i64.ctz (WASM): count leading zeros
• cttz.* (LLVM intrinsic)
• i32.popcnt, i64.popcnt (WASM): number of bits set to 1
• ctpop.* (LLVM intrinsic)

byte swap:

• bswap.* (LLVM intrinsics)
• rev rev16 revsh (ARM)

Floating-point-specific

WASM and LLVM provide abs(-olute-value), although LLVM abs is an intrinsic.

RISC-V and LLVM provide rounding in the form of conversion operations and rounding modes (LLVM requires the 'constrained' intrinsics to use these). WASM and LLVM provide rounding in the form of ceil, floor, trunc, nearest instructions (but WASM does not provide rounding mode control for other instructions; see [4] and [5]).

RISC-V and LLVM support IEEE exception flags and rounding modes (but LLVM only supports these with 'constrained' intrinsics. Because two platforms support this functionality it is included here, but note that some of the LLVM 'constrained' intrinsics are listed above, in the section 'Add, subtract, multiply, divide'.

Andreas Olofsson of Adapteva noted in a blog post that the Epiphany ISA does not include operations like RISC-V's exception flags, coercion operations, and rounding modes, because they were not needed for Epiphany's use case [6].

RISC-V provides an FCLASS instruction to report the attributes of a floating-point number. Andreas Olofsson of Adapteva said in a blog post that he felt that this instruction was "not essential" [7]. CIL provides ckfinite to check if a floating-point number is finite.

Fused multiply-add is provided by RISC-V and LLVM (but only as an LLVM intrinsic).

pow is provided by LLVM as an intrinsic and by LuaJIT?2.

some notes on the default rounding mode of other platforms: " WebAssembly? uses “non-stop” mode, and floating point exceptions are not otherwise observable. In particular, neither alternate floating point exception handling attributes nor the non-computational operators on status flags are supported. There is no observable difference between quiet and signalling NaN?. However, positive infinity, negative infinity, and NaN? are still always produced as result values to indicate overflow, invalid, and divide-by-zero conditions, as specified by IEEE 754-2008.

WebAssembly?