Wouldn't it be interesting if Oot could be a good choice for embedded systems too? This is not one of my main goals, but Lua is inspiring in that it seems it started out just trying to a small, portable, simple, language suitable for embedding into host applications, and it turned out to be suitable for running on low-end hardware too.
Oot has similar, if different, goals, so maybe we can think about targetting low-end hardware too. Our similar goals are: simplicity; embeddability into host applications, because it's hard to start using a new language if you have to write a project entirely in that language, but easier if you can start by adding new functionality to an existing project in the new language. Unlike Lua, we are not as concerned with performance, however.
PIC AVR ARM Intel Quark
ARM L1 cache
486 had 8K of L1 cache
Uses an ARM1176JZF-S processor, which was also used by the iPod Touch and many smartphones. (Broadcom BCM2835 SoC? with a GPU) at 700Mhz. The ARM1176JZF-S can have L1 cache configured from 4k to 64k.
This book claims that the Pi's L1 instruction cache is 16k and the L1 data cache is 16k.
Intel Quark SoC? X1000
16 Kbyte shared instruction and data L1 cache.
"The SoC? also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be configured to overlay regions of DRAM to provide low latency access to critical portions of system memory. For robustness, the contents of this on-die eSRAM are also ECC protected. "
Total memory size from 128 Mbyte to 2 Gbyte
ST Microelectronics STM32L151VB ultra-low-power 32 MHz ARM Cortex-M3 MCU -- http://www.ifixit.com/Teardown/Nest+Learning+Thermostat+2nd+Generation+Teardown/13818
ARM Cortex-M3 processor
Arduino Due: "The Due makes use of Atmel's SAM3U ARM-based process, which supports 32-bit instructions and runs at 96Mhz. The Due will have 256KB of Flash, 50KB of SRAM, five SPI buses, two I2C interfaces, five serial ports, 16 12-bit analog inputs and more. This is much more powerful than the current Uno or Mega.". Cortex M3
http://arduino.cc/en/Main/arduinoBoardDue says: 96 KBytes of SRAM. 512 KBytes of Flash memory for code.
" This operating system is stored in firmware, and runs on the baseband processor. As far as I know, this baseband RTOS is always entirely proprietary. For instance, the RTOS inside Qualcomm baseband processors (in this specific case, the MSM6280) is called AMSS, built upon their own proprietary REX kernel, and is made up of 69 concurrent tasks, handling everything from USB to GPS. It runs on an ARMv5 processor. "
http://beagleboard.org/Products/BeagleBone%20Black
Processor: AM335x 1GHz ARM® Cortex-A8
512MB DDR3 RAM
2GB 8-bit eMMC on-board flash storage
3D graphics accelerator
NEON floating-point accelerator
2x PRU 32-bit microcontrollersConnectivity
USB client for power & communications
USB host
Ethernet
HDMI
2x 46 pin headersSoftware Compatibility
Ångström Linux
Android
Ubuntu
Cloud9 IDE on Node.js w/ BoneScript library
plus much moreThe PRU 32-bit MCUs are:
http://elinux.org/Ti_AM33XX_PRUSSv2
8KB program memory
8KB data memory
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEADII.html
" The Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, and Cortex-M4 processors do not have any internal cache memory. However, it is possible for a SoC?