proj-oot-ootBootXThoughts

Some ideas for the compact encodings:

• stack addressing mode (SS; everything is a push/pop to the outstack),
• unify destination operand and one of the source operands (eg x = x + y)
• only use 4 regs: 1, SS, 4 (P0), 5 (T0)
• have every possible cp and ld between some set of registers (mb either the 4 above, or 1,2,3,4, or 1 thru 8 (4 takes up on the order of 16 opcodes * 2 instructions (cp and ld) = 32; 8 takes up on the order of 128 -- in both cases you could do something else for the 4 or 8 'cp x x's))
• have lds that mimic a bunch of fancy 'addr modes'

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bitwise and predication ideas:

• With 10 bits one can specify a single bit in any of the 32 registers. So with 20 bits one could do an and or an or between any two bits in the registers, If the destination operand is implied.
• if you have a distinguished bit register of 4 bits, then in 16 bits you can express two source operands (4 bits), plus a 2-in, 2-out gate (8 bits), plus two destination operands (4 bits). There's some redundancy here, but at least it's uniform.
• in 21 bits you can take 5 bits to specify a (4-bit) bit register out of 32 registers, then in the remaining 16 bits you can express two source operands (4 bits), plus a 2-in, 2-out function (8 bits), plus two destination operands (4 bits).
• in 21 bits you can take 5 bits to specify a (16-bit) bit register out of 32 registers, then in the remaining 16 bits you can express two operand bits (8 bits) plus a 2-in, 2-out gate (8 bits)
• in 21 bits, with a distinguished bit register of 32 bits you can take 3 bits to specify a 4-bit segment of this bit register, then 2 bits to select a predication bit within that segment, and then 16 bits for two source operands (4 bits), plus a 2-in, 2-out gate (8 bits), plus two destination operands (4 bits).
• in 21 bits, with two distinguished bit registers (for example, P0 and S0, or T0 and S0) of 16 bits each, you can take 1 bit to select which bit register to use, 2 bits to specify a 4-bit segment within that bit register, then 2 bits to select a predication bit within that segment, and then 16 bits for two source operands (4 bits), plus a 2-in, 2-out gate (8 bits), plus two destination operands (4 bits).

predication:

• if you have a single-bit predication bit register, with 1 predication specifier bit you can predicate
• with 2 predication specifier bits you could encode one of:
• predicate on one bit in a 4-bit bit register

load/store with two lanes of stop bits to order them: - 'relaxed' memory ordering except for the ordering imposed by the stop bits. There are two 'lanes' of dependencies (in addition to data dependencies, which are implied by the ISA and so don't need to be specified in each program). Any instruction has a dependency of all previous instructions which both have a stop bit in the same lane; that is to say, a stop bit in some lane means 'before executing this instruction, wait until every other concurrently executing previous instruction with a stop bit in this lane has finished'.

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