proj-oot-lowEndTargets-lowEndTargetsUnsorted4

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https://internalregister.github.io/2019/03/14/Homebrew-Console.html

64k program ram (of which 8k used by bootloader), z80

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Philips Hue Bridge 2.0

Philips Zigbee IP Bridge 2.0 (2.1) Availability: now

Manuf/OEM/ODM Lite-On 324131201801

FCC approval date: 28 July 2015 (Est.) initial retail price (in USD): $60 UPC: 046677458478 (UPC DB, On eBay) EAN: 046677455286 (UPC DB, On eBay) Country of manuf.: China

Amazon image

ASIN B016H0QZ7I (Flag of the United States.svg, On Amazon, On CCC, multiple uses) multiple revisions of this device, use caution

Type: home automation switch, IoT? hub

FCC ID: O3M324131201801, 2AGBW324131201801, 2AGBW3241312018AX Industry Canada ID: 10469A-BRIDGE, 20812-2018X

Power: 5.0 VDC, 1 A Connector type: barrel CPU1: Qualcomm Atheros QCA4531 (650 MHz) FLA1: 128 MiB? (Winbond W25N01GVZEIG) RAM1: 64 MiB? (Winbond W9751G6KB-25)

Expansion IFs: none specified

WI1 chip1: Qualcomm Atheros QCA4531 WI1 802dot11 protocols: bgn WI1 MIMO config: 2x2:2 WI1 antenna connector: none

ETH chip1: Qualcomm Atheros QCA4531 LAN speed: 10/100 LAN ports: 1

bgn

Additional chips 2.4GHz ZigBee?/802.15.4 SoC?/RF Transceiver (ARM Cortex-M0+ MCU);Atmel (Microchip);ATSAMR21E;Atmel, ATSAMR21E, 18A-F;;1; 2.4GHz ZigBee?/802.15.4 Power Amplifier;Skyworks;SE2438T;;1; USB to Serial Bridge Controller;Prolific;PL2303SA;;1;

Third party firmware supported: OpenWrt?

Flags: ZigBee?, Alexa AVS

802dot11 OUI: 00:17:88 CPU1 brand WI1 chip1 brand WI1 chip2 brand Philips Hue Bridge STMicro Texas Instruments Texas Instruments Philips Hue Bridge 2.0 Qualcomm Atheros Qualcomm Atheros For a list of all currently documented Qualcomm Atheros chipsets with specifications, see Qualcomm Atheros.

Philips Hue Smart Bridge

    Product page (2.0)  • Spec.

Ethernet-controlled Lighting controller and ZigBee? bridge,

    part of the Philips Hue system.

Compatible with Amazon Alexa, Apple HomeKit? and Google Assistant. Specifications

    Philips Hue Bridge 2.0 Teardown on Reddit (images)
    ZigBee: Atmel (Microchip) ATSAMR21E18A SoC
    @48MHz ARM Cortex-M0+ (32-bit) MCU
    2.4GHz RF Transceiver, 802.15.4, ZigBee
    MAC Address: 00:17:88 (Philips Lighting BV)
    Phillips Hue Dimmers Disassembled (images)

See also

    Philips Hue Bridge - ZigBee: TI CC2530
    Philips Hue Bridge 2.0 - IC: 10469A-BRIDGE,
    FCC ID: O3M324131201801 (2015-07-28)
    FCC ID: 2AGBW324131201801 (2015-11-12)
    Philips Hue Bridge 2.1 - Lite-On, IC: 20812-2018X,
    FCC ID: 2AGBW3241312018AX (2016-07-20)

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https://blog.adafruit.com/2016/06/14/teardown-of-a-philips-hue-led-lightbulb-with-zigbee-and-atmega2564-avr-iot-iotuesday/

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https://www.engadget.com/2019/03/18/nvidia-jetson-nano-ai-computer/

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rad-tolerant and rad-hard (i think these are terms without a precise defn but in this case i think the rad-hard one is a higher level of radiation tolerance/hardness):

https://www.microchip.com/wwwproducts/en/SAMV71Q21RT

https://www.microchip.com/wwwproducts/en/SAMRH71

the RH one doesn't have a datasheet but the other one has 2k flash and 384k RAM

ARM Cortex M7, 100 mhz (for the RH one)

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"MicroPython?, a version of the Python 3.4 programming language customized to run on low-power microcontrollers with as little as 16KB of RAM."

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https://hackaday.com/2019/02/04/openisa-launches-free-risc-v-vegaboard/

"72 MHz RISC-V RI5CY/ZERO-RISCY cores with up to 1280 KB and 384 KB of SRAM."

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https://www.phoronix.com/scan.php?page=news_item&px=MIPS-Open-Source-2019

http://linuxgizmos.com/this-under-6-sbc-runs-linux-on-risc-v-based-c-sky-chip/ Linux 4.20~5.0 kernel support for its new C-SKY CK810 SoC? design based on its new C-SKY ISA architecture. Now, Hangzhou C-SKY has launched a development board that runs Linux on a similar CK610M SoC?. The C-SKY Linux Development Board sells for 39-40 Yuan ($5.60 to $7.05) on Taobao and $19.50 to $21.50 on AliExpress?. 64MB DDR2 RAM and 4MB SPI flash for bootloader and media player code

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MAIX Development Boards with Sipeed M1 RISC-V AI Module Launched for $5 and Up (Crowdfunding) 8 MB general purpose SRAM including 5.9MB usable as AI SRAM memory Storage – micro SD card slot, 8MB SPI flash

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https://vocore.io/v2.html

MEMORY 128MB, DDR2, 166MHz STORAGE 16M NOR on board, support SDXC up to 2TB MIPS

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great awesome looking riscv risc-v fpga:

http://www.electronicdesign.com/embedded-revolution/risc-v-fpga-design-leaps-forward-mi-v

summarizing the interesting parts (for my purposes) of some of the above:

all of the three RISC-V cores noted have:

two of the 3 have:

and one of the 3 has:

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random IOT protocol: http://mqtt.org/

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even recent AVR lines have a multiply instruction now:

"Note that tinyAVR parts prior to the tinyAVR 1-Series are essentially completely different MCUs with a less-capable AVR core that has no multiplier."

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https://en.wikipedia.org/wiki/MIFARE

https://www.indiegogo.com/projects/sipeed-maix-the-world-first-risc-v-64-ai-module#/

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GAP8

https://www.cnx-software.com/2018/02/27/greenwaves-gap8-is-a-low-power-risc-v-iot-processor-optimized-for-artificial-intelligence-applications/

"Sub $15 machine vision and voice control solutions for consumer robotics"

" 1x extended RISC-V fabric controller core with 16 kB data and 4 kB instruction cache for system control 8x extended RISC-V compute cores with 64 kB shared data memory and 16 kB shared instruction cache "

"Another way to look at power consumption, is the company’s claim that the processor can classify a QVGA image every three minutes for 10 years on a small 3.6 Wh battery."

https://greenwaves-technologies.com/sdk-manuals/

" 1 + 8 high-performance cores: extended RISC-V ISA1 high performance micro-controller referred to as Fabric Controller or FC (150 MHz @ 1.0V; 250MHz @ 1.2V) 8 cores that execute in parallel for compute intensive tasks referred to as Cluster (87 MHz @ 1.0V; 170MHz @ 1.2V) Ultra low Power : maximum 25mA @ 1.0V

Memories: A level 2 Memory (512KB) for all the cores A level 1 Memory (64 KB) shared by all the cores in Cluster (0 wait state memory access) A level 1 memory (8 KB) owned by FC (0 wait state memory access) Memory Protection Unit HyperBus? Interface to connect external HyperFlash? or HyperRAM? "

https://www.cnx-software.com/2018/08/01/gapuino-gap8-risc-v-mcu-developer-kit-ai/ "GAPUINO GAP8 is a $229 RISC-V MCU Developer Kit for A.I. Applications

SoC? – GAP8 IoT? Application Processor with 8x RISC-V compute cores, 1x RISC-V fabric controller core delivering up to 200 MOPS at 1mW and >8 GOPS at a few tens of mW Memory / Storage – HyperBus? combo DRAM/Flash with 512 Mbit Flash + 64 Mbit DRAM; 256 Mbit Quad SPI flash

"

The design is based on RISC-V based Parallel Ultra Low Power (PULP) computing open-source platform.

https://www.cnx-software.com/2016/04/06/pulpino-open-source-risc-v-mcu-is-designed-for-iot-and-wearables/

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good detailed 2006 slide presentation on the old Cell architecture, including a list of synchronization commands (page 18)

https://arcb.csc.ncsu.edu/~mueller/cluster/ps3/workshop/Day1_03_CourseCode_L1T1H1-10_CellArchitecture.pdf

" Synchronization Commands

Lockline (Atomic Update) Commands: getllar- DMA 128 bytes from EA to LS and set Reservation putllc- Conditionally DMA 128 bytes from LS to EA putlluc- Unconditionally DMA 128 bytes from LS to EA

barrier- all previous commands complete before subsiquent commands are started mfcsync- Results of all previous commands in Tag groupare remotely visible mfceieio- Results of all preceding Puts commands in same group visible with respect to succeeding Get commands

Command Parameters

LSA- Local Store Address (32 bit) EA- Effective Address (32 or 64 bit) TS- Transfer Size (16 bytes to 16K bytes) LS- DMA List Size (8 bytes to 16 K bytes) TG- Tag Group(5 bit) CL- Cache Management / Bandwidth Class "

data bus is 16-byte (128-bit)

" Power Processor Element (PPE):

https://www.google.com/search?q=%22mfceieio%22+%22mfcsync%22+barrier+%22putlluc%22&oq=%22mfceieio%22+%22mfcsync%22+barrier+%22putlluc%22

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