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Freedom U500, Linux-capable, 1.5GH quad-core RV64GC SoC?: Jack Kang
Freedom Unleashed 500: 250M+ transistors, TSMC 28nm, high-performance integrated RISC-V SoC, U54MC RISC-V CPU Core Complex
1.5GHz+ SiFive E51/U53 CPU. 1xE51 (16KB L1I$, 8KB DTIM), 4 x U54. 32KB L1I$, 32KB L1D$.---
Celerity: An Open Source 511-core RISC-V Tiered Accelerator Fabric: Michael Taylor
511 RISC-V cores •5 Linux-capable RV64G Berkeley Rocket cores •496-coreRV32IMmesh tiled array “manycore” •10-core RV32IM mesh tiled array (low voltage)
The BaseJump? manycore architecture implements the RV32IM with a 5-stage pipeline (full forwarded, in-order, single issue). It has 4KB+4KB instruction and data scratchpads.
5 Berkeley Rocket Cores(https://github.com/freechipsproject/rocket-chip) •Generated from Chisel •RV64G ISA •5-stage, in-order, scalar processor •Double-precision floating point •I-Cache: 16KB 4-way assoc. •D-Cache: 16KB 4-way assoc
The tiled architecture 496 RISC-V Cores Scratchpad memory: 4KB for I Mem, 4KB for D Mem
Configuration Normalized Area (32nm)
Celerity Tile@16nm D-MEM = 4KB I-MEM = 4KB
OpenPiton? Tile@32nm L1 D-Cache = 8KB L1 I-Cache = 16KB L1.5/L2 Cache = 72KB 1.17 mm2
Raw Tile@180nm L1 D-Cache = 32KB L1 I-SRAM = 96KB
MIAOW GPU Compute Unit Lane @32nm VRF = 256KB SRF = 2KB
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Binarized Neural Networks •Training usually uses floating point, while inference usually uses lower precision weights and activations (often 8-bit or lower) to reduce implementation complexity •Rastergariet al. [3] and Courbariauxet al. [4] have recently shown single-bit precision weights and activations can achieve an accuracy of 89.8% on CIFAR-10
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the tiny KickSat? satellite project used MSP430s on its Sprite nanosatellites. The use Energia, a port of Arduino to MSP430s, to program it.
Aaccording to [1] and [2], the MSP430 used is:
It has 32KB Flash and 4KB RAM (both the specs and also KickSat?_SmallSat?