proj-oot-lowEndTargets-contemporaryLinuxCapableSystems

Embedded and low-end hardware survey: Contemporary Linux-capable systems

circa 2014

https://learn.adafruit.com/embedded-linux-board-comparison/overview

Rasberry Pi

Uses an ARM1176JZF-S processor, which was also used by the iPod Touch and many smartphones. (Broadcom BCM2835 SoC? with a GPU) at 700Mhz. The ARM1176JZF-S can have L1 cache configured from 4k to 64k.

This book claims that the Pi's L1 instruction cache is 16k and the L1 data cache is 16k.

Intel Quark

Intel Quark SoC? X1000

16 Kbyte shared instruction and data L1 cache.

"The SoC? also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be configured to overlay regions of DRAM to provide low latency access to critical portions of system memory. For robustness, the contents of this on-die eSRAM are also ECC protected. "

Total memory size from 128 Mbyte to 2 Gbyte

Intel Curie

" Curie, like Intel’s Edison, is designed to be an ultra-low power product SoC?, but the power consumption on Curie is going to make Edison’s dual-core Atom and 1GB of LPDDR3 look wasteful. Curie is based on the Quark SE core, which presumably offers the same instruction set compatibility as standard Quark (it’s essentially compatible with the original Pentium’s instruction set, minus MMX), but with just 80KB of onboard SRAM and 384KB of flash storage. The OS is listed only as an “open source real-time operating system” and connectivity is provided through low-energy Bluetooth. ... This new Curie module isn’t a direct competitor for anything in ARM’s standard product line — it’s going to go after ARM’s Cortex-M family of embedded microcontrollers. "

Arduino Tre

http://arstechnica.com/information-technology/2013/10/most-powerful-arduino-ever-has-arm-cortex-a8-chip-runs-full-linux/

Beaglebone

http://beagleboard.org/Products/BeagleBone%20Black

Processor: AM335x 1GHz ARM® Cortex-A8

    512MB DDR3 RAM
    2GB 8-bit eMMC on-board flash storage
    3D graphics accelerator
    NEON floating-point accelerator
    2x PRU 32-bit microcontrollers

Connectivity

    USB client for power & communications
    USB host
    Ethernet
    HDMI
    2x 46 pin headers

Software Compatibility

    Ångström Linux
    Android
    Ubuntu
    Cloud9 IDE on Node.js w/ BoneScript library
    plus much more

The PRU 32-bit MCUs are:

http://elinux.org/Ti_AM33XX_PRUSSv2

8KB program memory

8KB data memory

Core i3

not low-end but just to compare

http://www.hardwaresecrets.com/article/All-Core-i3-Models/951

32K L1 cache

Tegra 4

2013 ARM CPU used in tablets or mb mobile phones

Phones

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the CPU in my LG-D520 phone is a Krait: , which apparently is similar to ARM A15, a 4Ki L0 icache cache and a 4Ki L0 dcache and a 16Ki L1 icache cache and a 16Ki L1 dcache (L0 and L1 per core, i assume) and a 1k L2 cache (http://en.wikipedia.org/wiki/Krait_%28CPU%29 , http://ixbtlabs.com/articles3/mobile/snapdragon-s4-p2.html)

my previous phone was a Motorola Atrix (was it the Atrix 4g? MB860? probably. the following assumes that). ARM A9 http://www.anandtech.com/show/4165/the-motorola-atrix-4g-preview/5 http://en.wikipedia.org/wiki/Tegra#Tegra_2 http://www.nvidia.com/object/tegra-superchip.html with 32Ki / 32Ki L1 cache per core, and 1Mi L2 cache

before that was a G1, ARM A11, MSM7201A . can't get good numbers on L1 cache but http://forum.beyond3d.com/showpost.php?p=1552966&postcount=47 says "The MSM7201A did not just lack L2 cache - it didn't even have a FPU! All FP operations were done in software as if we were still in the 1980s. I'm not sure how significant this was for most handheld applications which are very integer-centric, but it does make it hard to judge the real benefit of the 256KB L2. I'm also not sure how much L1 cache the MSM7201A had - since they were penny pinching on everything else, I wouldn't be surprised if it was only 16/16KB."

currently there is a new budget smartphone phone OS, Firefox OS. Looking thru https://www.mozilla.org/en-US/firefox/os/devices/ for devices where the CPU is listed, we have Qualcomm Snapdragon MSM7227A , Qualcomm Snapdragon MSM7225A , Qualcomm Snapdragon 200 , MSM8210 ,

Out of these, the lowest end one listed on http://en.wikipedia.org/wiki/Snapdragon_%28system_on_chip%29 appears to be MSM7225, with ARM11 (ARMv6; i think ARM11 is earlier/worse than Cortex A5), according to http://tomkanok.wordpress.com/2011/07/13/qualcomm-msm7x25-msm7225-msm7625-and-msm7x27-msm7227-msm7667-cpu-in-mobile-phones/ these have 16+16ki L1 cache

so, if 16KiB? is the lowest we see here, what has/had an 8KiB? L1 cache?

http://superuser.com/questions/72209/why-has-the-size-of-l1-cache-not-increased-very-much-over-the-last-20-years says an Intel i486 had 8 KiB?. http://en.wikipedia.org/wiki/CPU_cache#Example confirms and adds that each cache block was 64 bytes.

In fact, the first mention in the History section of that Wikipedia page of an L1 cache with a specified size is the i486 8Ki cache: http://en.wikipedia.org/wiki/CPU_cache#In_x86_microprocessors . http://www.karbosguide.com/hardware/module3b2.htm thinks it was first.

so, in sum: everything smartphone-capable these days seems to have 16Ki or better L1 cache. In the past, the first L1 cache seemed to be 8 Ki, on the 486. Some things have a 4k "L0 cache", which apparently is an ill-defined term ( http://forum.beyond3d.com/showthread.php?t=54666 ).

the intel quark has a 16k "cache".

"The Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, and Cortex-M4 processors do not have any internal cache memory."

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the iPhone 1 had 128MB of RAM

one earlier iphone ("2g") had 16kb l1 cache (samsung S3C6400) (arm11 32-bit, so 4k items of 4 bytes apiece)

http://www.doc88.com/p-013708140603.html

an earlier iphone had no L2 cache, but a later one had 256k (so 64k items)

http://tooth2.blogspot.com/2010_03_01_archive.html

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" Spreadtrum Communications Inc. (Shanghai) announced it can supply its SC6821 baseband processor as a part of a reference design for a $25 smartphone that runs the Firefox operating system.

Spreadtrum and Mozilla have integrated the Firefox OS with several of Spreadtrum's WCDMA and EDGE smartphone chipsets, including the SC6821, which is thought to only support 2/2.5G.

In its press statement, Spreadtrum did not provide any technical details of the SC6821 or indicate how it differs from the previously announced SC6820 or SC6825. These are single- and dual-core Cortex-A5 based chips with Mali-400 GPUs, respectively. The SC6825 has 32-kbyte instruction and data caches and a 256-kbyte L2 cache.

The SC6821 is described as having a "low memory configuration" and a "high level of integration."

It will allow handset makers to create a phone with a 3.5-inch HVGA touchscreen, WiFi?, Bluetooth, FM radio and camera functions all controlled and accessed via the Firefox OS but at prices similar to much more minimally featured budget feature phones. "

http://pdadb.net/index.php?m=cpu&id=a6821&c=spreadtrum_sc6821

it's a 32-bit ARM Cortex-A5 MPcore (ARMv7-A ISA) system

in other works, the icache and dcache hold 8k words (ea. word is 32 bits, or 4 bytes). Somewhat unrelated: note that 64k bits is 8k bytes; but here we are talking about 8k words.

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TI OMAP

440 (kindle fire): http://www.tomshardware.com/reviews/amazon-kindle-fire-review,3076-9.html

vs nvidia tegra: http://www.extremetech.com/computing/95439-nvidia-tegra-2-vs-ti-omap-4-or-why-the-droid-bionic-uses-omap

http://en.wikipedia.org/wiki/OMAP#Products_using_OMAP_processors

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