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STM32F103 microcontroller
ARM Cortex M3 architecture
32-bit 72Mhz processor
128KB of Flash, 20KB of RAMi think that has either no instruction cache or an 4K or 8k one, but not at all sure.
the take-home for us is probably the amounts of flash and RAM. again, would be nice to fit the main interpreter in 16k or less, and that the upper limit is about 64k.
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The E64G401 Epiphany-IV 64-core 28nm Microprocessor has 32KB local (but shared) memory per core (so 32KB x 64 = 2MB total).
http://en.wikipedia.org/wiki/Adapteva
http://www.adapteva.com/wp-content/uploads/2013/06/e64g401_datasheet_4.13.6.14.pdf
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woah these are cheap:
https://en.wikipedia.org/wiki/Odroid
i think the Exynos 4412 has 32KB/32KB L1 Cache -- http://malideveloper.arm.com/develop-for-mali/development-platforms/hardkernel-odroid-u2-development-platform/
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http://linuxgizmos.com/intel-unveils-tiny-x86-minnowboard-max-open-sbc/
Raspberry Pi: $25/$35 BeagleBone? Black: $45 MinnowBoard? SBC: $99
" tdicola 13 hours ago
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This looks neat for people that want a cheap board to hack on embedded Linux. However for serious control of signal generation, acquisition, PWM, servos, etc. you really don't want to be running a multitasking OS. Something like the Beaglebone Black, with its dedicated 200mhz programmable units in addition to embedded Linux, is much more interesting for hackers and makers IMHO.
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" stonemetal 6 hours ago
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PRU-> programmable real time unit
BBB-> BeagleBone? Black
The BBB has an extra dual core processor that runs at 200Mhz. It is interesting because it is like the processor they teach you about in your intro to computer architecture classes, every instruction is a single cycle instruction. Since it is a co-processor(not running an OS but controllable from the BBB's OS) and execution of instructions is deterministic, it is a good choice for running hard real time code. "
" ah- 13 hours ago
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I wouldn't call the minnowboard a microcontroller, it's more similar to other single board computers like the Pandaboard and the odroid boards. And 2GB are already common for such boards, so 4GB are really not far off.
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outside1234 6 hours ago
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Does anyone know how the performance on something like this stacks up to something like the Raspberry Pi?
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wmf 5 hours ago
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A 1.4 GHz Silvermont must be many times faster than a 700 MHz ARM11.
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kqr2 14 hours ago
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Intel also has the Galileo board which is hardware and software pin-compatible with shields designed for the Arduino Uno* R3.
http://www.intel.com/content/www/us/en/intelligent-systems/g...
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makomk 11 hours ago
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The Galileo's one of those boards where it's very important to pay attention to the fine print. For example, the GPIO controller is hanging off a relatively slow I2C port, so access to GPIO is much, much slower than even the lowest-end Arduino. Also, it's a modified 486 which takes multiple clock cycles to carry out many instructions that are single-cycle on modern ARM, so it's not as fast at arithmetic as the clock speed would suggest.
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tdicola 14 hours ago
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Be careful though, the Galileo emulates AVR code and is orders of magnitude slower than a real Arduino. Don't expect to pick up any shield and make it work, unfortunately.
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jpwright 3 hours ago
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The Galileo actually only emulates a subset of the Arduino libraries. The AVR libraries themselves are, for the most part, not supported. This makes many popular libraries unusable even when hardware is not an issue.
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" elnate 14 hours ago
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How does this (note: the MinnowBoard? SBC) compare to a Raspberry Pi?
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vonmoltke 9 hours ago
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Comparing the $99 version to the B ($35):
Overall, probably worth the extra cost if you need the power and features. The question is, who does? I'm considering this for no other reason than I want a board in this form factor and power class that has SATA and PCIe.
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nullc 6 hours ago
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The RPI is really obscenely slow, far slower than the clock rate would suggest even for an arm. The RPI is pretty exciting as a microcontroller, though it's power usage is very high, but as a computer it's a real disappointment.
The real comparison should be with the odroid boards: http://hardkernel.com/main/products/prdt_info.php?g_code=G13... a quad arm (cortex-a9) at 1.7GHz with 2GB ram for ~$60.
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" Another note: In high school or my first year of college I told my dad that someday I'd own a 4K Data General NOVA. He said it cost as much as a down payment on an expensive house. I was stunned and told him I'd live in an apartment.
Why 4KB?
Because that was the minimum needed to run a higher level language. To me a computer had to have more than switches an lights. It had to be able to run programs.
" -- http://gizmodo.com/how-steve-wozniak-wrote-basic-for-the-original-apple-fr-1570573636/all
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about micropython:
chillingeffect 1 hour ago
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It appears from [0] that the chip of choice is the STM32F045RGT (datasheet [1]). This is from the Cortex M4f series, which includes such wonderful things as a hardware floating-point unit. That is wonderful news, although, this board appears to have no external memory, so it would be limited to 128kB.
[0] https://raw.githubusercontent.com/micropython/pyboard/master... [1] http://www.alldatasheet.com/datasheet-pdf/pdf/510587/STMICRO...
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--
" Micro Python has the following features:
More info at:
You can follow the progress and contribute at github:
www.github.com/micropython/micropython www.github.com/micropython/micropython-lib "
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according to "dec-11-ajpb-d pdp-11 basic programming manual", available from http://bitsavers.trailing-edge.com/pdf/dec/pdp11/basic/DEC-11-AJPB-D_PDP-11_BASIC_Programming_Manual_Dec70.pdf , or as text at https://archive.org/stream/bitsavers_decpdp11baASICProgrammingManualDec70_5936477/DEC-11-AJPB-D_PDP-11_BASIC_Programming_Manual_Dec70_djvu.txt ,
" A. 2 USER STORAGE REQUIREMENTS
BASIC can be run in the minimal 4K PDP-11/20 configuration. With the BASIC program in core, and deducting space reserved for the Bootstrap and Absolute Loaders, approximately 450 words are left for total user storage (program storage plus working storage) . "
i believe this 4k is 4k WORDS, and each word is two bytes, so BASIC takes up most of 8k, with about 900 bytes to spare; that is to say, BASIC takes about 7292 bytes, or just over 7k.
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according to http://lua-users.org/lists/lua-l/2007-11/msg00248.html , Lua was under 100k on cell phones, and according to http://www.lua.org/about.html , "Under Linux, the Lua interpreter built with all standard Lua libraries takes 182K...", and according to http://www.schulze-mueller.de/download/lua-poster-090207.pdf , Lua fit into 128k ROM.
http://www.luafaq.org/#T1.33 says "Embedding Lua will only add about 150-200K to your project, depending on what extra libraries are chosen. It was designed to be an extension language and it is straightforward to ensure that any user scripts operate in a 'safe' environment (see Sandboxing.) You do not even have to embed the compiler front-end of Lua, and just use the core with pre-compiled scripts. This can get the memory footprint down to about 40K."
and as noted above, there's also the eLua project:
" It's hard to give a precise answer to this, because this is not only dependable on the footprint of eLua or it's resource requirements but on the final user applications as well. As a general rule, for a 32-bit CPU, we recommend at least 256k of Flash and at least 64k of RAM. However, this isn't a strict requirement. A stripped down, integer-only version of eLua can definitely fit in 128k of Flash and depending on your type of application, 32k of RAM might prove just fine. We have built eLua for targets with less than 10K RAM but you can't do much than blinking an LED with them. It really largely depends on your needs. "
note that instruction sizes affect things somewhat here. if you measure things in words instead of bytes, then we have x86 variable length instruction sizes, compared with (i think?) PDP's 16-bit instruction size, and (i think) APPLE's 6502 8-bit opcodes. And newer machines require more bits per each address. Presumably then the same number of instructions may take up more room in newer machines.
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contiki:
http://www.wired.com/2014/06/contiki
" While Linux requires one megabyte of RAM, Contiki needs just a few kilobytes to run. Its inventor, Adam Dunkels, has managed to fit an entire operating system, including a graphical user interface, networking software, and a web browser into less than 30 kilobytes of space. That makes it much easier to run on small, low powered chips–exactly the sort of things used for connected devices–but it’s also been ported to many older systems like the Apple IIe and the Commodore 64. "
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interestingly, at the time Java was introduced, 'Java: an overview' says:
"The size of the basic interpreter and class support is about 30K bytes, adding the basic standard libraries and thread support (essentially a self-contained microkernel) brings it up to about 120K. "
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http://www.erlang.org/faq/implementations.html
" 8.9 Is Erlang small enough for embedded systems?
..
Rule of thumb: if the embedded system can run an operating system like linux, then it is possible to get current implementations of Erlang running on it with a reasonable amount of effort.
Getting Erlang to run on, say, an 8 bit CPU with 32kByte of RAM is not feasible.
People successfully run the Ericsson implementation of Erlang on systems with as little as 16MByte of RAM. It is reasonably straightforward to fit Erlang itself into 2MByte of persistant storage (e.g. a flash disk).
A 2MByte stripped Erlang system can include the beam emulator and almost all of the stdlib, sasl, kernel, inets and runtime_tools libraries, provided the libraries are compiled without debugging information and are compressed: "
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old Apple ][ 5.25inch floppy disks were apparently 140k per side.
Later there were mac 3.5 inch hard "floppy" disks that were apparently 400k, 800k (double-sided media) or 1.44 MB (double-sided, high-density)
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"tinyScheme, which is a BSD licensed, very small, very fast implementation of Scheme that can be compiled down into about a 20K executable if you know what you’re doing."
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(i already read this): http://www.digikey.com/en/articles/techzone/2012/jun/low-power-16-bit-mcus-expand-the-application-space-between-8--and-32-bit-options
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the CPU in my LG-D520 phone is a Krait: , which apparently is similar to ARM A15, a 4Ki L0 icache cache and a 4Ki L0 dcache and a 16Ki L1 icache cache and a 16Ki L1 dcache (L0 and L1 per core, i assume) and a 1k L2 cache (http://en.wikipedia.org/wiki/Krait_%28CPU%29 , http://ixbtlabs.com/articles3/mobile/snapdragon-s4-p2.html)
my previous phone was a Motorola Atrix (was it the Atrix 4g? MB860? probably. the following assumes that). ARM A9 http://www.anandtech.com/show/4165/the-motorola-atrix-4g-preview/5 http://en.wikipedia.org/wiki/Tegra#Tegra_2 http://www.nvidia.com/object/tegra-superchip.html with 32Ki / 32Ki L1 cache per core, and 1Mi L2 cache
before that was a G1, ARM A11, MSM7201A . can't get good numbers on L1 cache but http://forum.beyond3d.com/showpost.php?p=1552966&postcount=47 says "The MSM7201A did not just lack L2 cache - it didn't even have a FPU! All FP operations were done in software as if we were still in the 1980s. I'm not sure how significant this was for most handheld applications which are very integer-centric, but it does make it hard to judge the real benefit of the 256KB L2. I'm also not sure how much L1 cache the MSM7201A had - since they were penny pinching on everything else, I wouldn't be surprised if it was only 16/16KB."
currently there is a new budget smartphone phone OS, Firefox OS. Looking thru https://www.mozilla.org/en-US/firefox/os/devices/ for devices where the CPU is listed, we have Qualcomm Snapdragon MSM7227A , Qualcomm Snapdragon MSM7225A , Qualcomm Snapdragon 200 , MSM8210 ,
Out of these, the lowest end one listed on http://en.wikipedia.org/wiki/Snapdragon_%28system_on_chip%29 appears to be MSM7225, with ARM11 (ARMv6; i think ARM11 is earlier/worse than Cortex A5), according to http://tomkanok.wordpress.com/2011/07/13/qualcomm-msm7x25-msm7225-msm7625-and-msm7x27-msm7227-msm7667-cpu-in-mobile-phones/ these have 16+16ki L1 cache
so, if 16KiB? is the lowest we see here, what has/had an 8KiB? L1 cache?
http://superuser.com/questions/72209/why-has-the-size-of-l1-cache-not-increased-very-much-over-the-last-20-years says an Intel i486 had 8 KiB?. http://en.wikipedia.org/wiki/CPU_cache#Example confirms and adds that each cache block was 64 bytes.
In fact, the first mention in the History section of that Wikipedia page of an L1 cache with a specified size is the i486 8Ki cache: http://en.wikipedia.org/wiki/CPU_cache#In_x86_microprocessors . http://www.karbosguide.com/hardware/module3b2.htm thinks it was first.
so, in sum: everything smartphone-capable these days seems to have 16Ki or better L1 cache. In the past, the first L1 cache seemed to be 8 Ki, on the 486. Some things have a 4k "L0 cache", which apparently is an ill-defined term ( http://forum.beyond3d.com/showthread.php?t=54666 ).
the intel quark has a 16k "cache".
"The Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, and Cortex-M4 processors do not have any internal cache memory."
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apparently a lot of systems have 4k pages.
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a guy on the SENSORICA mailing list is using this chip for a soil moisture tracker:
http://www.atmel.com/devices/attiny85.aspx
512 bytes RAM, 8k flash
the chip costs about $1-$3
i'm only noting this because, although anecdotal, it's as an example of a real-world very low end use-case that i randomly heard about (i think it's not the lowest-end chip in its series, either, suggesting that someone thinks a real world application needs either 512 bytes RAM or 8k flash (or some other spec that the manufactorer thought would go well with those amounts))
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looks like consumer-priced massively parallel computers are still not available. Afaict the Pararella project is only contemplating a 64-CPU for $100, and that's the only one out there. Similarly, http://en.wikipedia.org/wiki/Intel_MIC has 32 cores. Some http://en.wikipedia.org/wiki/Nvidia_Tesla models at least offer on the order of 2048 cores -- but for a price of $3000.
so we're not getting much lower than $1/core yet in any offering. We need at least about 64k for $2000, or about $0.03/core. This is on the order of $0.01/core, so let's just say we need "a penny per core". Actually, that makes sense, because i was saying $2000 because a computer can cost $2000, but the CPU in that computer is much cheaper, on the order of $200 (retail). So $600 for the processors is already asking a lot.
If we have 64k processors at a penny each, that's about $655.36. At that point, enough hobbyists will be able to purchase one for applications to start being discovered at a reasonable rate.
The pararella 64-core is built off of this chip:
http://www.adapteva.com/epiphanyiv/
which has "2 MB On-Chip Distributed Shared Memory". They say:
" Memory System: The Epiphany memory architecture is based on a flat memory map in which each compute node has a small amount of local memory as a unique addressable slice of the total 32-bit address space. A processor can access its own local memory and other processors memory through regular load/store instructions, with the only difference being the latency and effective throughput of the transactions. The local memory system is comprised of 4 separate banks, allowing for simultaneous memory access by the instruction fetch engine, local load-store instructions, and by load/store transactions initiated by other processors within system. "
so that's 32k per chip
the new parallax propeller looks more minimal:
http://forums.parallax.com/showthread.php/155132-The-New-16-Cog-512KB-64-analog-I-O-Propeller-Chip
(32k per processor)
so it's anyone's guess how much k/core we'll have when we have 64k cores for $600, but between 8k and 32k is a good guess; more likely we can assume 32k.
so the Jasper runtime, including the really core libraries, shouldn't take more than half of this, 16k. sheesh, that's small. Still, it's double what the old PDP Basic version had to work with (slightly more, 'cause i think user memory had to fit in 8k along with the interpreter on that one). https://www.google.com/search?q=+basic+8k shows various BASIC versions fit in 8k. There's even some 4k BASICs: https://www.google.com/search?q=basic+4k
this suggests that if a Jasper VM or Jasper Assembly has (or initially has) fixed pseudo-pointer sizes, that 16-bit pseudo-pointers will be more than enough (especially since, if we make our unboxed primitive data elements of a uniform sizeof which is larger than 1 byte, 16k bytes of memory is less than 16 objects; e.g. 16k 16-bit objects take 32k bytes).
so, a 16-bit word size, and a corresponding 2^16 = 64k pseudo-memory size (ie limits such as no more than 64k local variables in a function, etc), seems reasonable for Jasper Assembly.
a parallax propeller cog is a 32-bit CPU, btw. So if our VM is 16 bits, we're undershooting that. Really, i just like 16 because 2^(2^2) = 16.
The Lua 5.1 VM 3-operand format operands are only 9 and 8 bits, so this is already bigger than that (although the 2-operand formats have an 8 bit operand and an 18-bit operand).
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" Spreadtrum Communications Inc. (Shanghai) announced it can supply its SC6821 baseband processor as a part of a reference design for a $25 smartphone that runs the Firefox operating system.
Spreadtrum and Mozilla have integrated the Firefox OS with several of Spreadtrum's WCDMA and EDGE smartphone chipsets, including the SC6821, which is thought to only support 2/2.5G.
In its press statement, Spreadtrum did not provide any technical details of the SC6821 or indicate how it differs from the previously announced SC6820 or SC6825. These are single- and dual-core Cortex-A5 based chips with Mali-400 GPUs, respectively. The SC6825 has 32-kbyte instruction and data caches and a 256-kbyte L2 cache.
The SC6821 is described as having a "low memory configuration" and a "high level of integration."
It will allow handset makers to create a phone with a 3.5-inch HVGA touchscreen, WiFi?, Bluetooth, FM radio and camera functions all controlled and accessed via the Firefox OS but at prices similar to much more minimally featured budget feature phones. "
http://pdadb.net/index.php?m=cpu&id=a6821&c=spreadtrum_sc6821
it's a 32-bit ARM Cortex-A5 MPcore (ARMv7-A ISA) system
in other works, the icache and dcache hold 8k words (ea. word is 32 bits, or 4 bytes). Somewhat unrelated: note that 64k bits is 8k bytes; but here we are talking about 8k words.
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could also look at the resources available to each processor or even each 'thread' within the GPU in low-end GPGPU systems. The Intel integrated graphics (e.g. integrated into the package or die of the CPU) GPUs supported the OpenCL?