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How a d-latch works

There's an interactive picture of a d-latch at:

http://www.simplecpu.com/memory.html

When the bottom input is 1, the output matches the top input.

When the bottom input is 0, output remains whatever it last was when the bottom input was "on".

How?

Name the components of the diagram like this. topInput, bottomInput, topLeftNAND, bottomLeftNAND, topRightNAND, bottomRightNAND, output. In between the left and the right NAND gates, we have the outputs of topLeftNAND and of bottomLeftNAND.

When bottomInput is 1

bottomInput sends a 1 to each of the two left NAND gates. A NAND gate with one input set to be 1 acts as a NOT gate on the other input. So, topLeftNAND is acting as a NOT gate on topInput, and bottomLeftNAND gate is acting as a NOT gate on output of topLeftNAND. So, the values being output by the left NAND gates are:

topLeftNAND = not(topInput) bottomLeftNAND = not(not(topInput)) = topInput

Note that these two values are the negation of each other; one of them will be 0 and the other will be 1.

Note that diagram is symmetric from now on (ie. everything to the right of the left NAND gates)

Now, either the output of topLeftNAND or the output of bottomLeftNAND must be 0. Without loss of generality (due to the symmetry), assume that the topLeftNAND is 0 and the bottomLeftNAND is 1 (this will occur when topInput is 1).

So topRightNAND will be getting at least one 0 input. A NAND gate getting a 0 input must always output 1. So topRightNAND is outputting 1. So the output is 1. And the feedback input to bottomRightNAND is 1. bottomRightNAND's inputs are therefore 1 and 1. So the feedback input to topLeftNAND is 0.

When bottomInput is 0

Now bottomInput is sending a 0 to each of topLeftNAND and topRightNAND. So both topLeftNAND and topRightNAND must output 1 (disregarding topInput). So topRightNand is getting a 1, and a feedback input; and bottomRightNAND is also getting a 1, and a feedback input. So topRightNAND will output the negation of its feedback input, and likewise for bottomRightNAND.

So what are the feedback inputs? Well, if the bottomInput was 1 a moment ago and we just switched it to 0, then one of the feedback inputs will be 0, and the other will be 1. If, when bottomInput was 1, topInput was 0, then the top feedback input will be 1 and the bottom feedback input will be 0, and if topInput was 1, then the top feedback input will be 0 and the bottom feedback input will be 1.

So, if the topInput was 0, then the top feedback input will be 1 and the bottom feedback input will be 0, so the topRightNAND's inputs will be 1 and 1, so it will output 0, and the output will be 0, and the bottom feedback input will be 0, and the bottomRightNAND's inputs will be 0 and 1, so it will output 1, so the top feedback input will be 1. Which is the same state for the feedback inputs as they used to be, so we have reached a steady state, and the output will persist at 0.

Similarly, if the topInput was 1, the same line of reasoning as in the previous paragraph shows that the output will persist at 1.

(side note: what if the bottomInput was 0 initially, and the feedback inputs started out initially as either both 0 or both 1? The inputs to both right NAND gates would then be identical; a 1, and whatever the feedbacks started out as. Therefore, both right NAND gates would act as NOT gates on the feedback inputs. But this would change both of the feedback inputs to their opposite. But the same situation now pertains, so the feedback inputs would flip again. This would continue indefinitely. In the real world, however, the change in polarity of the feedback inputs would not always happen at precisely the same time, so eventually there would be a moment where one of the feedback inputs was 0 and the other was 1; but this is a steady state, so the flickering would stop and the system would persist in that state)